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authorAlex Deucher <alexdeucher@gmail.com>2009-12-23 13:21:58 -0500
committerDave Airlie <airlied@redhat.com>2010-02-08 18:32:28 -0500
commit0ec0e74f784ca08eab0354ab1dada46924c39b73 (patch)
treedc2a3d67fc5009f385b43bf9198427ff9050e39c /drivers/gpu/drm/radeon/radeon_atombios.c
parent845db70da0bd285813b25bb522a0281f28efbf89 (diff)
drm/radeon/kms: add a power state type based on power state flags
The idea is to flag a power state with a certain type and use that type to decide on what state to select. On r6xx+, we select a state and then transition between clock modes in that state. On pre-r6xx, we transition between states directly. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/radeon_atombios.c')
-rw-r--r--drivers/gpu/drm/radeon/radeon_atombios.c78
1 files changed, 78 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c b/drivers/gpu/drm/radeon/radeon_atombios.c
index e8fbae6395c7..b55012fedb94 100644
--- a/drivers/gpu/drm/radeon/radeon_atombios.c
+++ b/drivers/gpu/drm/radeon/radeon_atombios.c
@@ -1465,7 +1465,25 @@ void radeon_atombios_get_power_modes(struct radeon_device *rdev)
1465 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id = 1465 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
1466 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex; 1466 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex;
1467 } 1467 }
1468 /* order matters! */
1469 if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
1470 rdev->pm.power_state[state_index].type =
1471 POWER_STATE_TYPE_POWERSAVE;
1472 if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
1473 rdev->pm.power_state[state_index].type =
1474 POWER_STATE_TYPE_BATTERY;
1475 if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
1476 rdev->pm.power_state[state_index].type =
1477 POWER_STATE_TYPE_BATTERY;
1478 if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
1479 rdev->pm.power_state[state_index].type =
1480 POWER_STATE_TYPE_BALANCED;
1481 if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN)
1482 rdev->pm.power_state[state_index].type =
1483 POWER_STATE_TYPE_PERFORMANCE;
1468 if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) { 1484 if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
1485 rdev->pm.power_state[state_index].type =
1486 POWER_STATE_TYPE_DEFAULT;
1469 rdev->pm.default_power_state = &rdev->pm.power_state[state_index]; 1487 rdev->pm.default_power_state = &rdev->pm.power_state[state_index];
1470 rdev->pm.current_power_state = &rdev->pm.power_state[state_index]; 1488 rdev->pm.current_power_state = &rdev->pm.power_state[state_index];
1471 rdev->pm.power_state[state_index].default_clock_mode = 1489 rdev->pm.power_state[state_index].default_clock_mode =
@@ -1513,7 +1531,28 @@ void radeon_atombios_get_power_modes(struct radeon_device *rdev)
1513 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id = 1531 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
1514 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex; 1532 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex;
1515 } 1533 }
1534 /* order matters! */
1535 if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
1536 rdev->pm.power_state[state_index].type =
1537 POWER_STATE_TYPE_POWERSAVE;
1538 if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
1539 rdev->pm.power_state[state_index].type =
1540 POWER_STATE_TYPE_BATTERY;
1541 if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
1542 rdev->pm.power_state[state_index].type =
1543 POWER_STATE_TYPE_BATTERY;
1544 if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
1545 rdev->pm.power_state[state_index].type =
1546 POWER_STATE_TYPE_BALANCED;
1547 if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN)
1548 rdev->pm.power_state[state_index].type =
1549 POWER_STATE_TYPE_PERFORMANCE;
1550 if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE)
1551 rdev->pm.power_state[state_index].type =
1552 POWER_STATE_TYPE_BALANCED;
1516 if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) { 1553 if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
1554 rdev->pm.power_state[state_index].type =
1555 POWER_STATE_TYPE_DEFAULT;
1517 rdev->pm.default_power_state = &rdev->pm.power_state[state_index]; 1556 rdev->pm.default_power_state = &rdev->pm.power_state[state_index];
1518 rdev->pm.current_power_state = &rdev->pm.power_state[state_index]; 1557 rdev->pm.current_power_state = &rdev->pm.power_state[state_index];
1519 rdev->pm.power_state[state_index].default_clock_mode = 1558 rdev->pm.power_state[state_index].default_clock_mode =
@@ -1567,7 +1606,28 @@ void radeon_atombios_get_power_modes(struct radeon_device *rdev)
1567 power_info->info_3.asPowerPlayInfo[i].ucVDDCI_VoltageDropIndex; 1606 power_info->info_3.asPowerPlayInfo[i].ucVDDCI_VoltageDropIndex;
1568 } 1607 }
1569 } 1608 }
1609 /* order matters! */
1610 if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
1611 rdev->pm.power_state[state_index].type =
1612 POWER_STATE_TYPE_POWERSAVE;
1613 if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
1614 rdev->pm.power_state[state_index].type =
1615 POWER_STATE_TYPE_BATTERY;
1616 if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
1617 rdev->pm.power_state[state_index].type =
1618 POWER_STATE_TYPE_BATTERY;
1619 if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
1620 rdev->pm.power_state[state_index].type =
1621 POWER_STATE_TYPE_BALANCED;
1622 if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN)
1623 rdev->pm.power_state[state_index].type =
1624 POWER_STATE_TYPE_PERFORMANCE;
1625 if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE)
1626 rdev->pm.power_state[state_index].type =
1627 POWER_STATE_TYPE_BALANCED;
1570 if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) { 1628 if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
1629 rdev->pm.power_state[state_index].type =
1630 POWER_STATE_TYPE_DEFAULT;
1571 rdev->pm.default_power_state = &rdev->pm.power_state[state_index]; 1631 rdev->pm.default_power_state = &rdev->pm.power_state[state_index];
1572 rdev->pm.current_power_state = &rdev->pm.power_state[state_index]; 1632 rdev->pm.current_power_state = &rdev->pm.power_state[state_index];
1573 rdev->pm.power_state[state_index].default_clock_mode = 1633 rdev->pm.power_state[state_index].default_clock_mode =
@@ -1655,7 +1715,23 @@ void radeon_atombios_get_power_modes(struct radeon_device *rdev)
1655 rdev->pm.power_state[state_index].non_clock_info.pcie_lanes = 1715 rdev->pm.power_state[state_index].non_clock_info.pcie_lanes =
1656 ((misc & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> 1716 ((misc & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >>
1657 ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1; 1717 ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1;
1718 switch (misc2 & ATOM_PPLIB_CLASSIFICATION_UI_MASK) {
1719 case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY:
1720 rdev->pm.power_state[state_index].type =
1721 POWER_STATE_TYPE_BATTERY;
1722 break;
1723 case ATOM_PPLIB_CLASSIFICATION_UI_BALANCED:
1724 rdev->pm.power_state[state_index].type =
1725 POWER_STATE_TYPE_BALANCED;
1726 break;
1727 case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE:
1728 rdev->pm.power_state[state_index].type =
1729 POWER_STATE_TYPE_PERFORMANCE;
1730 break;
1731 }
1658 if (misc2 & ATOM_PPLIB_CLASSIFICATION_BOOT) { 1732 if (misc2 & ATOM_PPLIB_CLASSIFICATION_BOOT) {
1733 rdev->pm.power_state[state_index].type =
1734 POWER_STATE_TYPE_DEFAULT;
1659 rdev->pm.default_power_state = &rdev->pm.power_state[state_index]; 1735 rdev->pm.default_power_state = &rdev->pm.power_state[state_index];
1660 rdev->pm.current_power_state = &rdev->pm.power_state[state_index]; 1736 rdev->pm.current_power_state = &rdev->pm.power_state[state_index];
1661 rdev->pm.power_state[state_index].default_clock_mode = 1737 rdev->pm.power_state[state_index].default_clock_mode =
@@ -1673,6 +1749,8 @@ void radeon_atombios_get_power_modes(struct radeon_device *rdev)
1673 1749
1674 if (rdev->pm.default_power_state == NULL) { 1750 if (rdev->pm.default_power_state == NULL) {
1675 /* add the default mode */ 1751 /* add the default mode */
1752 rdev->pm.power_state[state_index].type =
1753 POWER_STATE_TYPE_DEFAULT;
1676 rdev->pm.power_state[state_index].num_clock_modes = 1; 1754 rdev->pm.power_state[state_index].num_clock_modes = 1;
1677 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk; 1755 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
1678 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk; 1756 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-11 18:01:44 -0500