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authorAlex Deucher <alexdeucher@gmail.com>2010-04-22 14:03:55 -0400
committerDave Airlie <airlied@redhat.com>2010-05-18 04:20:58 -0400
commita48b9b4edb8bb87deb13b9f088a595cf71457b69 (patch)
tree2cfe4156f911042a6c3943ee98503d452941dd92 /drivers/gpu/drm/radeon/radeon_atombios.c
parentbae6b5627387a950a8faf366d6027bd0a7a93078 (diff)
drm/radeon/kms/pm: add asic specific callbacks for getting power state (v2)
This also simplifies the code and enables reclocking with multiple heads active by tracking whether the power states are single or multi-head capable. Eventually, we will want to select a power state based on external factors (AC/DC state, user selection, etc.). (v2) Update for evergreen Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/radeon_atombios.c')
-rw-r--r--drivers/gpu/drm/radeon/radeon_atombios.c91
1 files changed, 41 insertions, 50 deletions
diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c b/drivers/gpu/drm/radeon/radeon_atombios.c
index aa0a973a8af2..dbfb837d224c 100644
--- a/drivers/gpu/drm/radeon/radeon_atombios.c
+++ b/drivers/gpu/drm/radeon/radeon_atombios.c
@@ -1489,7 +1489,7 @@ void radeon_atombios_get_power_modes(struct radeon_device *rdev)
1489 int state_index = 0, mode_index = 0; 1489 int state_index = 0, mode_index = 0;
1490 struct radeon_i2c_bus_rec i2c_bus; 1490 struct radeon_i2c_bus_rec i2c_bus;
1491 1491
1492 rdev->pm.default_power_state = NULL; 1492 rdev->pm.default_power_state_index = -1;
1493 1493
1494 if (atom_parse_data_header(mode_info->atom_context, index, NULL, 1494 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1495 &frev, &crev, &data_offset)) { 1495 &frev, &crev, &data_offset)) {
@@ -1520,12 +1520,6 @@ void radeon_atombios_get_power_modes(struct radeon_device *rdev)
1520 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) || 1520 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
1521 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0)) 1521 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
1522 continue; 1522 continue;
1523 /* skip overclock modes for now */
1524 if ((rdev->pm.power_state[state_index].clock_info[0].mclk >
1525 rdev->clock.default_mclk + RADEON_MODE_OVERCLOCK_MARGIN) ||
1526 (rdev->pm.power_state[state_index].clock_info[0].sclk >
1527 rdev->clock.default_sclk + RADEON_MODE_OVERCLOCK_MARGIN))
1528 continue;
1529 rdev->pm.power_state[state_index].non_clock_info.pcie_lanes = 1523 rdev->pm.power_state[state_index].non_clock_info.pcie_lanes =
1530 power_info->info.asPowerPlayInfo[i].ucNumPciELanes; 1524 power_info->info.asPowerPlayInfo[i].ucNumPciELanes;
1531 misc = le32_to_cpu(power_info->info.asPowerPlayInfo[i].ulMiscInfo); 1525 misc = le32_to_cpu(power_info->info.asPowerPlayInfo[i].ulMiscInfo);
@@ -1547,6 +1541,7 @@ void radeon_atombios_get_power_modes(struct radeon_device *rdev)
1547 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id = 1541 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
1548 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex; 1542 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex;
1549 } 1543 }
1544 rdev->pm.power_state[state_index].flags = RADEON_PM_SINGLE_DISPLAY_ONLY;
1550 /* order matters! */ 1545 /* order matters! */
1551 if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE) 1546 if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
1552 rdev->pm.power_state[state_index].type = 1547 rdev->pm.power_state[state_index].type =
@@ -1560,15 +1555,20 @@ void radeon_atombios_get_power_modes(struct radeon_device *rdev)
1560 if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN) 1555 if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
1561 rdev->pm.power_state[state_index].type = 1556 rdev->pm.power_state[state_index].type =
1562 POWER_STATE_TYPE_BALANCED; 1557 POWER_STATE_TYPE_BALANCED;
1563 if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) 1558 if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) {
1564 rdev->pm.power_state[state_index].type = 1559 rdev->pm.power_state[state_index].type =
1565 POWER_STATE_TYPE_PERFORMANCE; 1560 POWER_STATE_TYPE_PERFORMANCE;
1561 rdev->pm.power_state[state_index].flags &=
1562 ~RADEON_PM_SINGLE_DISPLAY_ONLY;
1563 }
1566 if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) { 1564 if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
1567 rdev->pm.power_state[state_index].type = 1565 rdev->pm.power_state[state_index].type =
1568 POWER_STATE_TYPE_DEFAULT; 1566 POWER_STATE_TYPE_DEFAULT;
1569 rdev->pm.default_power_state = &rdev->pm.power_state[state_index]; 1567 rdev->pm.default_power_state_index = state_index;
1570 rdev->pm.power_state[state_index].default_clock_mode = 1568 rdev->pm.power_state[state_index].default_clock_mode =
1571 &rdev->pm.power_state[state_index].clock_info[0]; 1569 &rdev->pm.power_state[state_index].clock_info[0];
1570 rdev->pm.power_state[state_index].flags &=
1571 ~RADEON_PM_SINGLE_DISPLAY_ONLY;
1572 } 1572 }
1573 state_index++; 1573 state_index++;
1574 break; 1574 break;
@@ -1582,12 +1582,6 @@ void radeon_atombios_get_power_modes(struct radeon_device *rdev)
1582 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) || 1582 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
1583 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0)) 1583 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
1584 continue; 1584 continue;
1585 /* skip overclock modes for now */
1586 if ((rdev->pm.power_state[state_index].clock_info[0].mclk >
1587 rdev->clock.default_mclk + RADEON_MODE_OVERCLOCK_MARGIN) ||
1588 (rdev->pm.power_state[state_index].clock_info[0].sclk >
1589 rdev->clock.default_sclk + RADEON_MODE_OVERCLOCK_MARGIN))
1590 continue;
1591 rdev->pm.power_state[state_index].non_clock_info.pcie_lanes = 1585 rdev->pm.power_state[state_index].non_clock_info.pcie_lanes =
1592 power_info->info_2.asPowerPlayInfo[i].ucNumPciELanes; 1586 power_info->info_2.asPowerPlayInfo[i].ucNumPciELanes;
1593 misc = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo); 1587 misc = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo);
@@ -1610,6 +1604,7 @@ void radeon_atombios_get_power_modes(struct radeon_device *rdev)
1610 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id = 1604 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
1611 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex; 1605 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex;
1612 } 1606 }
1607 rdev->pm.power_state[state_index].flags = RADEON_PM_SINGLE_DISPLAY_ONLY;
1613 /* order matters! */ 1608 /* order matters! */
1614 if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE) 1609 if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
1615 rdev->pm.power_state[state_index].type = 1610 rdev->pm.power_state[state_index].type =
@@ -1623,18 +1618,26 @@ void radeon_atombios_get_power_modes(struct radeon_device *rdev)
1623 if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN) 1618 if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
1624 rdev->pm.power_state[state_index].type = 1619 rdev->pm.power_state[state_index].type =
1625 POWER_STATE_TYPE_BALANCED; 1620 POWER_STATE_TYPE_BALANCED;
1626 if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) 1621 if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) {
1627 rdev->pm.power_state[state_index].type = 1622 rdev->pm.power_state[state_index].type =
1628 POWER_STATE_TYPE_PERFORMANCE; 1623 POWER_STATE_TYPE_PERFORMANCE;
1624 rdev->pm.power_state[state_index].flags &=
1625 ~RADEON_PM_SINGLE_DISPLAY_ONLY;
1626 }
1629 if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE) 1627 if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE)
1630 rdev->pm.power_state[state_index].type = 1628 rdev->pm.power_state[state_index].type =
1631 POWER_STATE_TYPE_BALANCED; 1629 POWER_STATE_TYPE_BALANCED;
1630 if (misc2 & ATOM_PM_MISCINFO2_MULTI_DISPLAY_SUPPORT)
1631 rdev->pm.power_state[state_index].flags &=
1632 ~RADEON_PM_SINGLE_DISPLAY_ONLY;
1632 if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) { 1633 if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
1633 rdev->pm.power_state[state_index].type = 1634 rdev->pm.power_state[state_index].type =
1634 POWER_STATE_TYPE_DEFAULT; 1635 POWER_STATE_TYPE_DEFAULT;
1635 rdev->pm.default_power_state = &rdev->pm.power_state[state_index]; 1636 rdev->pm.default_power_state_index = state_index;
1636 rdev->pm.power_state[state_index].default_clock_mode = 1637 rdev->pm.power_state[state_index].default_clock_mode =
1637 &rdev->pm.power_state[state_index].clock_info[0]; 1638 &rdev->pm.power_state[state_index].clock_info[0];
1639 rdev->pm.power_state[state_index].flags &=
1640 ~RADEON_PM_SINGLE_DISPLAY_ONLY;
1638 } 1641 }
1639 state_index++; 1642 state_index++;
1640 break; 1643 break;
@@ -1648,12 +1651,6 @@ void radeon_atombios_get_power_modes(struct radeon_device *rdev)
1648 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) || 1651 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
1649 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0)) 1652 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
1650 continue; 1653 continue;
1651 /* skip overclock modes for now */
1652 if ((rdev->pm.power_state[state_index].clock_info[0].mclk >
1653 rdev->clock.default_mclk + RADEON_MODE_OVERCLOCK_MARGIN) ||
1654 (rdev->pm.power_state[state_index].clock_info[0].sclk >
1655 rdev->clock.default_sclk + RADEON_MODE_OVERCLOCK_MARGIN))
1656 continue;
1657 rdev->pm.power_state[state_index].non_clock_info.pcie_lanes = 1654 rdev->pm.power_state[state_index].non_clock_info.pcie_lanes =
1658 power_info->info_3.asPowerPlayInfo[i].ucNumPciELanes; 1655 power_info->info_3.asPowerPlayInfo[i].ucNumPciELanes;
1659 misc = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo); 1656 misc = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo);
@@ -1682,6 +1679,7 @@ void radeon_atombios_get_power_modes(struct radeon_device *rdev)
1682 power_info->info_3.asPowerPlayInfo[i].ucVDDCI_VoltageDropIndex; 1679 power_info->info_3.asPowerPlayInfo[i].ucVDDCI_VoltageDropIndex;
1683 } 1680 }
1684 } 1681 }
1682 rdev->pm.power_state[state_index].flags = RADEON_PM_SINGLE_DISPLAY_ONLY;
1685 /* order matters! */ 1683 /* order matters! */
1686 if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE) 1684 if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
1687 rdev->pm.power_state[state_index].type = 1685 rdev->pm.power_state[state_index].type =
@@ -1695,16 +1693,19 @@ void radeon_atombios_get_power_modes(struct radeon_device *rdev)
1695 if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN) 1693 if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
1696 rdev->pm.power_state[state_index].type = 1694 rdev->pm.power_state[state_index].type =
1697 POWER_STATE_TYPE_BALANCED; 1695 POWER_STATE_TYPE_BALANCED;
1698 if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) 1696 if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) {
1699 rdev->pm.power_state[state_index].type = 1697 rdev->pm.power_state[state_index].type =
1700 POWER_STATE_TYPE_PERFORMANCE; 1698 POWER_STATE_TYPE_PERFORMANCE;
1699 rdev->pm.power_state[state_index].flags &=
1700 ~RADEON_PM_SINGLE_DISPLAY_ONLY;
1701 }
1701 if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE) 1702 if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE)
1702 rdev->pm.power_state[state_index].type = 1703 rdev->pm.power_state[state_index].type =
1703 POWER_STATE_TYPE_BALANCED; 1704 POWER_STATE_TYPE_BALANCED;
1704 if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) { 1705 if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
1705 rdev->pm.power_state[state_index].type = 1706 rdev->pm.power_state[state_index].type =
1706 POWER_STATE_TYPE_DEFAULT; 1707 POWER_STATE_TYPE_DEFAULT;
1707 rdev->pm.default_power_state = &rdev->pm.power_state[state_index]; 1708 rdev->pm.default_power_state_index = state_index;
1708 rdev->pm.power_state[state_index].default_clock_mode = 1709 rdev->pm.power_state[state_index].default_clock_mode =
1709 &rdev->pm.power_state[state_index].clock_info[0]; 1710 &rdev->pm.power_state[state_index].clock_info[0];
1710 } 1711 }
@@ -1713,12 +1714,14 @@ void radeon_atombios_get_power_modes(struct radeon_device *rdev)
1713 } 1714 }
1714 } 1715 }
1715 /* last mode is usually default */ 1716 /* last mode is usually default */
1716 if (!rdev->pm.default_power_state) { 1717 if (rdev->pm.default_power_state_index == -1) {
1717 rdev->pm.power_state[state_index - 1].type = 1718 rdev->pm.power_state[state_index - 1].type =
1718 POWER_STATE_TYPE_DEFAULT; 1719 POWER_STATE_TYPE_DEFAULT;
1719 rdev->pm.default_power_state = &rdev->pm.power_state[state_index - 1]; 1720 rdev->pm.default_power_state_index = state_index - 1;
1720 rdev->pm.power_state[state_index - 1].default_clock_mode = 1721 rdev->pm.power_state[state_index - 1].default_clock_mode =
1721 &rdev->pm.power_state[state_index - 1].clock_info[0]; 1722 &rdev->pm.power_state[state_index - 1].clock_info[0];
1723 rdev->pm.power_state[state_index].flags &=
1724 ~RADEON_PM_SINGLE_DISPLAY_ONLY;
1722 } 1725 }
1723 } else { 1726 } else {
1724 /* add the i2c bus for thermal/fan chip */ 1727 /* add the i2c bus for thermal/fan chip */
@@ -1774,10 +1777,6 @@ void radeon_atombios_get_power_modes(struct radeon_device *rdev)
1774 /* skip invalid modes */ 1777 /* skip invalid modes */
1775 if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0) 1778 if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0)
1776 continue; 1779 continue;
1777 /* skip overclock modes for now */
1778 if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk >
1779 rdev->clock.default_sclk + RADEON_MODE_OVERCLOCK_MARGIN)
1780 continue;
1781 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type = 1780 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
1782 VOLTAGE_SW; 1781 VOLTAGE_SW;
1783 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage = 1782 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
@@ -1801,12 +1800,6 @@ void radeon_atombios_get_power_modes(struct radeon_device *rdev)
1801 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) || 1800 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) ||
1802 (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0)) 1801 (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0))
1803 continue; 1802 continue;
1804 /* skip overclock modes for now */
1805 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk >
1806 rdev->clock.default_mclk + RADEON_MODE_OVERCLOCK_MARGIN) ||
1807 (rdev->pm.power_state[state_index].clock_info[mode_index].sclk >
1808 rdev->clock.default_sclk + RADEON_MODE_OVERCLOCK_MARGIN))
1809 continue;
1810 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type = 1803 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
1811 VOLTAGE_SW; 1804 VOLTAGE_SW;
1812 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage = 1805 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
@@ -1831,12 +1824,6 @@ void radeon_atombios_get_power_modes(struct radeon_device *rdev)
1831 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) || 1824 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) ||
1832 (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0)) 1825 (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0))
1833 continue; 1826 continue;
1834 /* skip overclock modes for now */
1835 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk >
1836 rdev->clock.default_mclk + RADEON_MODE_OVERCLOCK_MARGIN) ||
1837 (rdev->pm.power_state[state_index].clock_info[mode_index].sclk >
1838 rdev->clock.default_sclk + RADEON_MODE_OVERCLOCK_MARGIN))
1839 continue;
1840 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type = 1827 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
1841 VOLTAGE_SW; 1828 VOLTAGE_SW;
1842 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage = 1829 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
@@ -1865,10 +1852,14 @@ void radeon_atombios_get_power_modes(struct radeon_device *rdev)
1865 POWER_STATE_TYPE_PERFORMANCE; 1852 POWER_STATE_TYPE_PERFORMANCE;
1866 break; 1853 break;
1867 } 1854 }
1855 rdev->pm.power_state[state_index].flags = 0;
1856 if (misc & ATOM_PPLIB_SINGLE_DISPLAY_ONLY)
1857 rdev->pm.power_state[state_index].flags |=
1858 RADEON_PM_SINGLE_DISPLAY_ONLY;
1868 if (misc2 & ATOM_PPLIB_CLASSIFICATION_BOOT) { 1859 if (misc2 & ATOM_PPLIB_CLASSIFICATION_BOOT) {
1869 rdev->pm.power_state[state_index].type = 1860 rdev->pm.power_state[state_index].type =
1870 POWER_STATE_TYPE_DEFAULT; 1861 POWER_STATE_TYPE_DEFAULT;
1871 rdev->pm.default_power_state = &rdev->pm.power_state[state_index]; 1862 rdev->pm.default_power_state_index = state_index;
1872 rdev->pm.power_state[state_index].default_clock_mode = 1863 rdev->pm.power_state[state_index].default_clock_mode =
1873 &rdev->pm.power_state[state_index].clock_info[mode_index - 1]; 1864 &rdev->pm.power_state[state_index].clock_info[mode_index - 1];
1874 } 1865 }
@@ -1876,10 +1867,10 @@ void radeon_atombios_get_power_modes(struct radeon_device *rdev)
1876 } 1867 }
1877 } 1868 }
1878 /* first mode is usually default */ 1869 /* first mode is usually default */
1879 if (!rdev->pm.default_power_state) { 1870 if (rdev->pm.default_power_state_index == -1) {
1880 rdev->pm.power_state[0].type = 1871 rdev->pm.power_state[0].type =
1881 POWER_STATE_TYPE_DEFAULT; 1872 POWER_STATE_TYPE_DEFAULT;
1882 rdev->pm.default_power_state = &rdev->pm.power_state[0]; 1873 rdev->pm.default_power_state_index = 0;
1883 rdev->pm.power_state[0].default_clock_mode = 1874 rdev->pm.power_state[0].default_clock_mode =
1884 &rdev->pm.power_state[0].clock_info[0]; 1875 &rdev->pm.power_state[0].clock_info[0];
1885 } 1876 }
@@ -1898,15 +1889,15 @@ void radeon_atombios_get_power_modes(struct radeon_device *rdev)
1898 rdev->pm.power_state[state_index].non_clock_info.pcie_lanes = radeon_get_pcie_lanes(rdev); 1889 rdev->pm.power_state[state_index].non_clock_info.pcie_lanes = radeon_get_pcie_lanes(rdev);
1899 else 1890 else
1900 rdev->pm.power_state[state_index].non_clock_info.pcie_lanes = 16; 1891 rdev->pm.power_state[state_index].non_clock_info.pcie_lanes = 16;
1901 rdev->pm.default_power_state = &rdev->pm.power_state[state_index]; 1892 rdev->pm.default_power_state_index = state_index;
1893 rdev->pm.power_state[state_index].flags = 0;
1902 state_index++; 1894 state_index++;
1903 } 1895 }
1904 1896
1905 rdev->pm.num_power_states = state_index; 1897 rdev->pm.num_power_states = state_index;
1906 1898
1907 rdev->pm.current_power_state = rdev->pm.default_power_state; 1899 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
1908 rdev->pm.current_clock_mode = 1900 rdev->pm.current_clock_mode_index = 0;
1909 rdev->pm.default_power_state->default_clock_mode;
1910} 1901}
1911 1902
1912void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable) 1903void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable)
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-08 01:27:34 -0500