aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/gpu/drm/radeon/radeon_asic.h
diff options
context:
space:
mode:
authorJerome Glisse <jglisse@redhat.com>2009-10-01 04:12:06 -0400
committerDave Airlie <airlied@redhat.com>2009-10-01 18:51:49 -0400
commitd4550907157d8b3d5286157c15f1200c44842269 (patch)
tree0e9733667b3608ca44929650c8431878134c0315 /drivers/gpu/drm/radeon/radeon_asic.h
parent207bf9e90cd40f91d4662127b8ae3b64e6b101c4 (diff)
drm/radeon/kms: Convert R100 to new init path (V2)
New init path allow to simply asic initialization and make easier to trace what happen on each different asic. We are removing most callback. More cleanup should happen latter to remove even more callback. Also cleanup register specific to R100,RV200,RV250. Version 2 correct the placement on IGP of the VRAM inside GPU address space to match the stollen RAM placement of IGP. Signed-off-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/radeon_asic.h')
-rw-r--r--drivers/gpu/drm/radeon/radeon_asic.h50
1 files changed, 21 insertions, 29 deletions
diff --git a/drivers/gpu/drm/radeon/radeon_asic.h b/drivers/gpu/drm/radeon/radeon_asic.h
index 72562cf372b7..39f1bb656e61 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.h
+++ b/drivers/gpu/drm/radeon/radeon_asic.h
@@ -41,27 +41,16 @@ void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
41/* 41/*
42 * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 42 * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
43 */ 43 */
44int r100_init(struct radeon_device *rdev); 44extern int r100_init(struct radeon_device *rdev);
45int r200_init(struct radeon_device *rdev); 45extern void r100_fini(struct radeon_device *rdev);
46extern int r100_suspend(struct radeon_device *rdev);
47extern int r100_resume(struct radeon_device *rdev);
46uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg); 48uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg);
47void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 49void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
48void r100_errata(struct radeon_device *rdev);
49void r100_vram_info(struct radeon_device *rdev);
50int r100_gpu_reset(struct radeon_device *rdev); 50int r100_gpu_reset(struct radeon_device *rdev);
51int r100_mc_init(struct radeon_device *rdev);
52void r100_mc_fini(struct radeon_device *rdev);
53u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc); 51u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc);
54int r100_wb_init(struct radeon_device *rdev);
55void r100_wb_fini(struct radeon_device *rdev);
56int r100_pci_gart_init(struct radeon_device *rdev);
57void r100_pci_gart_fini(struct radeon_device *rdev);
58int r100_pci_gart_enable(struct radeon_device *rdev);
59void r100_pci_gart_disable(struct radeon_device *rdev);
60void r100_pci_gart_tlb_flush(struct radeon_device *rdev); 52void r100_pci_gart_tlb_flush(struct radeon_device *rdev);
61int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); 53int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
62int r100_cp_init(struct radeon_device *rdev, unsigned ring_size);
63void r100_cp_fini(struct radeon_device *rdev);
64void r100_cp_disable(struct radeon_device *rdev);
65void r100_cp_commit(struct radeon_device *rdev); 54void r100_cp_commit(struct radeon_device *rdev);
66void r100_ring_start(struct radeon_device *rdev); 55void r100_ring_start(struct radeon_device *rdev);
67int r100_irq_set(struct radeon_device *rdev); 56int r100_irq_set(struct radeon_device *rdev);
@@ -87,27 +76,30 @@ int r100_ring_test(struct radeon_device *rdev);
87 76
88static struct radeon_asic r100_asic = { 77static struct radeon_asic r100_asic = {
89 .init = &r100_init, 78 .init = &r100_init,
90 .errata = &r100_errata, 79 .fini = &r100_fini,
91 .vram_info = &r100_vram_info, 80 .suspend = &r100_suspend,
81 .resume = &r100_resume,
82 .errata = NULL,
83 .vram_info = NULL,
92 .gpu_reset = &r100_gpu_reset, 84 .gpu_reset = &r100_gpu_reset,
93 .mc_init = &r100_mc_init, 85 .mc_init = NULL,
94 .mc_fini = &r100_mc_fini, 86 .mc_fini = NULL,
95 .wb_init = &r100_wb_init, 87 .wb_init = NULL,
96 .wb_fini = &r100_wb_fini, 88 .wb_fini = NULL,
97 .gart_init = &r100_pci_gart_init, 89 .gart_init = NULL,
98 .gart_fini = &r100_pci_gart_fini, 90 .gart_fini = NULL,
99 .gart_enable = &r100_pci_gart_enable, 91 .gart_enable = NULL,
100 .gart_disable = &r100_pci_gart_disable, 92 .gart_disable = NULL,
101 .gart_tlb_flush = &r100_pci_gart_tlb_flush, 93 .gart_tlb_flush = &r100_pci_gart_tlb_flush,
102 .gart_set_page = &r100_pci_gart_set_page, 94 .gart_set_page = &r100_pci_gart_set_page,
103 .cp_init = &r100_cp_init, 95 .cp_init = NULL,
104 .cp_fini = &r100_cp_fini, 96 .cp_fini = NULL,
105 .cp_disable = &r100_cp_disable, 97 .cp_disable = NULL,
106 .cp_commit = &r100_cp_commit, 98 .cp_commit = &r100_cp_commit,
107 .ring_start = &r100_ring_start, 99 .ring_start = &r100_ring_start,
108 .ring_test = &r100_ring_test, 100 .ring_test = &r100_ring_test,
109 .ring_ib_execute = &r100_ring_ib_execute, 101 .ring_ib_execute = &r100_ring_ib_execute,
110 .ib_test = &r100_ib_test, 102 .ib_test = NULL,
111 .irq_set = &r100_irq_set, 103 .irq_set = &r100_irq_set,
112 .irq_process = &r100_irq_process, 104 .irq_process = &r100_irq_process,
113 .get_vblank_counter = &r100_get_vblank_counter, 105 .get_vblank_counter = &r100_get_vblank_counter,