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authorRafał Miłecki <zajec5@gmail.com>2009-11-02 18:53:02 -0500
committerDave Airlie <airlied@redhat.com>2009-11-05 23:13:25 -0500
commit7433874e31f7f2e6e942b12012790565731d0f4a (patch)
treeb67ed1c06492f5d0831762ab8b3a9267b65b94da /drivers/gpu/drm/radeon/radeon_asic.h
parenta3fa6320ce964f799388b152a1b0f6e2c3b32a7f (diff)
drm/radeon/kms: add debugfs for power management for AtomBIOS devices
Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/radeon_asic.h')
-rw-r--r--drivers/gpu/drm/radeon/radeon_asic.h23
1 files changed, 23 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/radeon_asic.h b/drivers/gpu/drm/radeon/radeon_asic.h
index d38f99632827..94991edc839f 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.h
+++ b/drivers/gpu/drm/radeon/radeon_asic.h
@@ -31,10 +31,13 @@
31/* 31/*
32 * common functions 32 * common functions
33 */ 33 */
34uint32_t radeon_legacy_get_engine_clock(struct radeon_device *rdev);
34void radeon_legacy_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock); 35void radeon_legacy_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock);
35void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable); 36void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
36 37
38uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev);
37void radeon_atom_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock); 39void radeon_atom_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock);
40uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev);
38void radeon_atom_set_memory_clock(struct radeon_device *rdev, uint32_t mem_clock); 41void radeon_atom_set_memory_clock(struct radeon_device *rdev, uint32_t mem_clock);
39void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable); 42void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
40 43
@@ -93,7 +96,9 @@ static struct radeon_asic r100_asic = {
93 .copy_blit = &r100_copy_blit, 96 .copy_blit = &r100_copy_blit,
94 .copy_dma = NULL, 97 .copy_dma = NULL,
95 .copy = &r100_copy_blit, 98 .copy = &r100_copy_blit,
99 .get_engine_clock = &radeon_legacy_get_engine_clock,
96 .set_engine_clock = &radeon_legacy_set_engine_clock, 100 .set_engine_clock = &radeon_legacy_set_engine_clock,
101 .get_memory_clock = NULL,
97 .set_memory_clock = NULL, 102 .set_memory_clock = NULL,
98 .set_pcie_lanes = NULL, 103 .set_pcie_lanes = NULL,
99 .set_clock_gating = &radeon_legacy_set_clock_gating, 104 .set_clock_gating = &radeon_legacy_set_clock_gating,
@@ -145,7 +150,9 @@ static struct radeon_asic r300_asic = {
145 .copy_blit = &r100_copy_blit, 150 .copy_blit = &r100_copy_blit,
146 .copy_dma = &r300_copy_dma, 151 .copy_dma = &r300_copy_dma,
147 .copy = &r100_copy_blit, 152 .copy = &r100_copy_blit,
153 .get_engine_clock = &radeon_legacy_get_engine_clock,
148 .set_engine_clock = &radeon_legacy_set_engine_clock, 154 .set_engine_clock = &radeon_legacy_set_engine_clock,
155 .get_memory_clock = NULL,
149 .set_memory_clock = NULL, 156 .set_memory_clock = NULL,
150 .set_pcie_lanes = &rv370_set_pcie_lanes, 157 .set_pcie_lanes = &rv370_set_pcie_lanes,
151 .set_clock_gating = &radeon_legacy_set_clock_gating, 158 .set_clock_gating = &radeon_legacy_set_clock_gating,
@@ -181,7 +188,9 @@ static struct radeon_asic r420_asic = {
181 .copy_blit = &r100_copy_blit, 188 .copy_blit = &r100_copy_blit,
182 .copy_dma = &r300_copy_dma, 189 .copy_dma = &r300_copy_dma,
183 .copy = &r100_copy_blit, 190 .copy = &r100_copy_blit,
191 .get_engine_clock = &radeon_atom_get_engine_clock,
184 .set_engine_clock = &radeon_atom_set_engine_clock, 192 .set_engine_clock = &radeon_atom_set_engine_clock,
193 .get_memory_clock = &radeon_atom_get_memory_clock,
185 .set_memory_clock = &radeon_atom_set_memory_clock, 194 .set_memory_clock = &radeon_atom_set_memory_clock,
186 .set_pcie_lanes = &rv370_set_pcie_lanes, 195 .set_pcie_lanes = &rv370_set_pcie_lanes,
187 .set_clock_gating = &radeon_atom_set_clock_gating, 196 .set_clock_gating = &radeon_atom_set_clock_gating,
@@ -222,7 +231,9 @@ static struct radeon_asic rs400_asic = {
222 .copy_blit = &r100_copy_blit, 231 .copy_blit = &r100_copy_blit,
223 .copy_dma = &r300_copy_dma, 232 .copy_dma = &r300_copy_dma,
224 .copy = &r100_copy_blit, 233 .copy = &r100_copy_blit,
234 .get_engine_clock = &radeon_legacy_get_engine_clock,
225 .set_engine_clock = &radeon_legacy_set_engine_clock, 235 .set_engine_clock = &radeon_legacy_set_engine_clock,
236 .get_memory_clock = NULL,
226 .set_memory_clock = NULL, 237 .set_memory_clock = NULL,
227 .set_pcie_lanes = NULL, 238 .set_pcie_lanes = NULL,
228 .set_clock_gating = &radeon_legacy_set_clock_gating, 239 .set_clock_gating = &radeon_legacy_set_clock_gating,
@@ -267,7 +278,9 @@ static struct radeon_asic rs600_asic = {
267 .copy_blit = &r100_copy_blit, 278 .copy_blit = &r100_copy_blit,
268 .copy_dma = &r300_copy_dma, 279 .copy_dma = &r300_copy_dma,
269 .copy = &r100_copy_blit, 280 .copy = &r100_copy_blit,
281 .get_engine_clock = &radeon_atom_get_engine_clock,
270 .set_engine_clock = &radeon_atom_set_engine_clock, 282 .set_engine_clock = &radeon_atom_set_engine_clock,
283 .get_memory_clock = &radeon_atom_get_memory_clock,
271 .set_memory_clock = &radeon_atom_set_memory_clock, 284 .set_memory_clock = &radeon_atom_set_memory_clock,
272 .set_pcie_lanes = NULL, 285 .set_pcie_lanes = NULL,
273 .set_clock_gating = &radeon_atom_set_clock_gating, 286 .set_clock_gating = &radeon_atom_set_clock_gating,
@@ -305,7 +318,9 @@ static struct radeon_asic rs690_asic = {
305 .copy_blit = &r100_copy_blit, 318 .copy_blit = &r100_copy_blit,
306 .copy_dma = &r300_copy_dma, 319 .copy_dma = &r300_copy_dma,
307 .copy = &r300_copy_dma, 320 .copy = &r300_copy_dma,
321 .get_engine_clock = &radeon_atom_get_engine_clock,
308 .set_engine_clock = &radeon_atom_set_engine_clock, 322 .set_engine_clock = &radeon_atom_set_engine_clock,
323 .get_memory_clock = &radeon_atom_get_memory_clock,
309 .set_memory_clock = &radeon_atom_set_memory_clock, 324 .set_memory_clock = &radeon_atom_set_memory_clock,
310 .set_pcie_lanes = NULL, 325 .set_pcie_lanes = NULL,
311 .set_clock_gating = &radeon_atom_set_clock_gating, 326 .set_clock_gating = &radeon_atom_set_clock_gating,
@@ -349,7 +364,9 @@ static struct radeon_asic rv515_asic = {
349 .copy_blit = &r100_copy_blit, 364 .copy_blit = &r100_copy_blit,
350 .copy_dma = &r300_copy_dma, 365 .copy_dma = &r300_copy_dma,
351 .copy = &r100_copy_blit, 366 .copy = &r100_copy_blit,
367 .get_engine_clock = &radeon_atom_get_engine_clock,
352 .set_engine_clock = &radeon_atom_set_engine_clock, 368 .set_engine_clock = &radeon_atom_set_engine_clock,
369 .get_memory_clock = &radeon_atom_get_memory_clock,
353 .set_memory_clock = &radeon_atom_set_memory_clock, 370 .set_memory_clock = &radeon_atom_set_memory_clock,
354 .set_pcie_lanes = &rv370_set_pcie_lanes, 371 .set_pcie_lanes = &rv370_set_pcie_lanes,
355 .set_clock_gating = &radeon_atom_set_clock_gating, 372 .set_clock_gating = &radeon_atom_set_clock_gating,
@@ -384,7 +401,9 @@ static struct radeon_asic r520_asic = {
384 .copy_blit = &r100_copy_blit, 401 .copy_blit = &r100_copy_blit,
385 .copy_dma = &r300_copy_dma, 402 .copy_dma = &r300_copy_dma,
386 .copy = &r100_copy_blit, 403 .copy = &r100_copy_blit,
404 .get_engine_clock = &radeon_atom_get_engine_clock,
387 .set_engine_clock = &radeon_atom_set_engine_clock, 405 .set_engine_clock = &radeon_atom_set_engine_clock,
406 .get_memory_clock = &radeon_atom_get_memory_clock,
388 .set_memory_clock = &radeon_atom_set_memory_clock, 407 .set_memory_clock = &radeon_atom_set_memory_clock,
389 .set_pcie_lanes = &rv370_set_pcie_lanes, 408 .set_pcie_lanes = &rv370_set_pcie_lanes,
390 .set_clock_gating = &radeon_atom_set_clock_gating, 409 .set_clock_gating = &radeon_atom_set_clock_gating,
@@ -445,7 +464,9 @@ static struct radeon_asic r600_asic = {
445 .copy_blit = &r600_copy_blit, 464 .copy_blit = &r600_copy_blit,
446 .copy_dma = &r600_copy_blit, 465 .copy_dma = &r600_copy_blit,
447 .copy = &r600_copy_blit, 466 .copy = &r600_copy_blit,
467 .get_engine_clock = &radeon_atom_get_engine_clock,
448 .set_engine_clock = &radeon_atom_set_engine_clock, 468 .set_engine_clock = &radeon_atom_set_engine_clock,
469 .get_memory_clock = &radeon_atom_get_memory_clock,
449 .set_memory_clock = &radeon_atom_set_memory_clock, 470 .set_memory_clock = &radeon_atom_set_memory_clock,
450 .set_pcie_lanes = NULL, 471 .set_pcie_lanes = NULL,
451 .set_clock_gating = &radeon_atom_set_clock_gating, 472 .set_clock_gating = &radeon_atom_set_clock_gating,
@@ -481,7 +502,9 @@ static struct radeon_asic rv770_asic = {
481 .copy_blit = &r600_copy_blit, 502 .copy_blit = &r600_copy_blit,
482 .copy_dma = &r600_copy_blit, 503 .copy_dma = &r600_copy_blit,
483 .copy = &r600_copy_blit, 504 .copy = &r600_copy_blit,
505 .get_engine_clock = &radeon_atom_get_engine_clock,
484 .set_engine_clock = &radeon_atom_set_engine_clock, 506 .set_engine_clock = &radeon_atom_set_engine_clock,
507 .get_memory_clock = &radeon_atom_get_memory_clock,
485 .set_memory_clock = &radeon_atom_set_memory_clock, 508 .set_memory_clock = &radeon_atom_set_memory_clock,
486 .set_pcie_lanes = NULL, 509 .set_pcie_lanes = NULL,
487 .set_clock_gating = &radeon_atom_set_clock_gating, 510 .set_clock_gating = &radeon_atom_set_clock_gating,