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authorJerome Glisse <jglisse@redhat.com>2009-10-01 12:02:11 -0400
committerDave Airlie <airlied@redhat.com>2009-10-01 19:33:46 -0400
commit62a8ea3f7bb61e5f92db0a648b7cc566852c36ec (patch)
tree3ffefdbe940c66591dd4863ccf3a766498bf5100 /drivers/gpu/drm/radeon/radeon_asic.h
parentc010f8000a925e08d84d9391e13dd297b9fdc393 (diff)
drm/radeon/kms: Remove old init path as no hw use it anymore
This remove old init path and allow code cleanup, now all hw use the new init path, see top of radeon.h for description of this. Signed-off-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/radeon_asic.h')
-rw-r--r--drivers/gpu/drm/radeon/radeon_asic.h138
1 files changed, 0 insertions, 138 deletions
diff --git a/drivers/gpu/drm/radeon/radeon_asic.h b/drivers/gpu/drm/radeon/radeon_asic.h
index 7bc86a6aa5d6..d38f99632827 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.h
+++ b/drivers/gpu/drm/radeon/radeon_asic.h
@@ -71,7 +71,6 @@ int r100_set_surface_reg(struct radeon_device *rdev, int reg,
71int r100_clear_surface_reg(struct radeon_device *rdev, int reg); 71int r100_clear_surface_reg(struct radeon_device *rdev, int reg);
72void r100_bandwidth_update(struct radeon_device *rdev); 72void r100_bandwidth_update(struct radeon_device *rdev);
73void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 73void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
74int r100_ib_test(struct radeon_device *rdev);
75int r100_ring_test(struct radeon_device *rdev); 74int r100_ring_test(struct radeon_device *rdev);
76 75
77static struct radeon_asic r100_asic = { 76static struct radeon_asic r100_asic = {
@@ -79,27 +78,13 @@ static struct radeon_asic r100_asic = {
79 .fini = &r100_fini, 78 .fini = &r100_fini,
80 .suspend = &r100_suspend, 79 .suspend = &r100_suspend,
81 .resume = &r100_resume, 80 .resume = &r100_resume,
82 .errata = NULL,
83 .vram_info = NULL,
84 .gpu_reset = &r100_gpu_reset, 81 .gpu_reset = &r100_gpu_reset,
85 .mc_init = NULL,
86 .mc_fini = NULL,
87 .wb_init = NULL,
88 .wb_fini = NULL,
89 .gart_init = NULL,
90 .gart_fini = NULL,
91 .gart_enable = NULL,
92 .gart_disable = NULL,
93 .gart_tlb_flush = &r100_pci_gart_tlb_flush, 82 .gart_tlb_flush = &r100_pci_gart_tlb_flush,
94 .gart_set_page = &r100_pci_gart_set_page, 83 .gart_set_page = &r100_pci_gart_set_page,
95 .cp_init = NULL,
96 .cp_fini = NULL,
97 .cp_disable = NULL,
98 .cp_commit = &r100_cp_commit, 84 .cp_commit = &r100_cp_commit,
99 .ring_start = &r100_ring_start, 85 .ring_start = &r100_ring_start,
100 .ring_test = &r100_ring_test, 86 .ring_test = &r100_ring_test,
101 .ring_ib_execute = &r100_ring_ib_execute, 87 .ring_ib_execute = &r100_ring_ib_execute,
102 .ib_test = NULL,
103 .irq_set = &r100_irq_set, 88 .irq_set = &r100_irq_set,
104 .irq_process = &r100_irq_process, 89 .irq_process = &r100_irq_process,
105 .get_vblank_counter = &r100_get_vblank_counter, 90 .get_vblank_counter = &r100_get_vblank_counter,
@@ -145,27 +130,13 @@ static struct radeon_asic r300_asic = {
145 .fini = &r300_fini, 130 .fini = &r300_fini,
146 .suspend = &r300_suspend, 131 .suspend = &r300_suspend,
147 .resume = &r300_resume, 132 .resume = &r300_resume,
148 .errata = NULL,
149 .vram_info = NULL,
150 .gpu_reset = &r300_gpu_reset, 133 .gpu_reset = &r300_gpu_reset,
151 .mc_init = NULL,
152 .mc_fini = NULL,
153 .wb_init = NULL,
154 .wb_fini = NULL,
155 .gart_init = NULL,
156 .gart_fini = NULL,
157 .gart_enable = NULL,
158 .gart_disable = NULL,
159 .gart_tlb_flush = &r100_pci_gart_tlb_flush, 134 .gart_tlb_flush = &r100_pci_gart_tlb_flush,
160 .gart_set_page = &r100_pci_gart_set_page, 135 .gart_set_page = &r100_pci_gart_set_page,
161 .cp_init = NULL,
162 .cp_fini = NULL,
163 .cp_disable = NULL,
164 .cp_commit = &r100_cp_commit, 136 .cp_commit = &r100_cp_commit,
165 .ring_start = &r300_ring_start, 137 .ring_start = &r300_ring_start,
166 .ring_test = &r100_ring_test, 138 .ring_test = &r100_ring_test,
167 .ring_ib_execute = &r100_ring_ib_execute, 139 .ring_ib_execute = &r100_ring_ib_execute,
168 .ib_test = NULL,
169 .irq_set = &r100_irq_set, 140 .irq_set = &r100_irq_set,
170 .irq_process = &r100_irq_process, 141 .irq_process = &r100_irq_process,
171 .get_vblank_counter = &r100_get_vblank_counter, 142 .get_vblank_counter = &r100_get_vblank_counter,
@@ -195,25 +166,13 @@ static struct radeon_asic r420_asic = {
195 .fini = &r420_fini, 166 .fini = &r420_fini,
196 .suspend = &r420_suspend, 167 .suspend = &r420_suspend,
197 .resume = &r420_resume, 168 .resume = &r420_resume,
198 .errata = NULL,
199 .vram_info = NULL,
200 .gpu_reset = &r300_gpu_reset, 169 .gpu_reset = &r300_gpu_reset,
201 .mc_init = NULL,
202 .mc_fini = NULL,
203 .wb_init = NULL,
204 .wb_fini = NULL,
205 .gart_enable = NULL,
206 .gart_disable = NULL,
207 .gart_tlb_flush = &rv370_pcie_gart_tlb_flush, 170 .gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
208 .gart_set_page = &rv370_pcie_gart_set_page, 171 .gart_set_page = &rv370_pcie_gart_set_page,
209 .cp_init = NULL,
210 .cp_fini = NULL,
211 .cp_disable = NULL,
212 .cp_commit = &r100_cp_commit, 172 .cp_commit = &r100_cp_commit,
213 .ring_start = &r300_ring_start, 173 .ring_start = &r300_ring_start,
214 .ring_test = &r100_ring_test, 174 .ring_test = &r100_ring_test,
215 .ring_ib_execute = &r100_ring_ib_execute, 175 .ring_ib_execute = &r100_ring_ib_execute,
216 .ib_test = NULL,
217 .irq_set = &r100_irq_set, 176 .irq_set = &r100_irq_set,
218 .irq_process = &r100_irq_process, 177 .irq_process = &r100_irq_process,
219 .get_vblank_counter = &r100_get_vblank_counter, 178 .get_vblank_counter = &r100_get_vblank_counter,
@@ -248,27 +207,13 @@ static struct radeon_asic rs400_asic = {
248 .fini = &rs400_fini, 207 .fini = &rs400_fini,
249 .suspend = &rs400_suspend, 208 .suspend = &rs400_suspend,
250 .resume = &rs400_resume, 209 .resume = &rs400_resume,
251 .errata = NULL,
252 .vram_info = NULL,
253 .gpu_reset = &r300_gpu_reset, 210 .gpu_reset = &r300_gpu_reset,
254 .mc_init = NULL,
255 .mc_fini = NULL,
256 .wb_init = NULL,
257 .wb_fini = NULL,
258 .gart_init = NULL,
259 .gart_fini = NULL,
260 .gart_enable = NULL,
261 .gart_disable = NULL,
262 .gart_tlb_flush = &rs400_gart_tlb_flush, 211 .gart_tlb_flush = &rs400_gart_tlb_flush,
263 .gart_set_page = &rs400_gart_set_page, 212 .gart_set_page = &rs400_gart_set_page,
264 .cp_init = NULL,
265 .cp_fini = NULL,
266 .cp_disable = NULL,
267 .cp_commit = &r100_cp_commit, 213 .cp_commit = &r100_cp_commit,
268 .ring_start = &r300_ring_start, 214 .ring_start = &r300_ring_start,
269 .ring_test = &r100_ring_test, 215 .ring_test = &r100_ring_test,
270 .ring_ib_execute = &r100_ring_ib_execute, 216 .ring_ib_execute = &r100_ring_ib_execute,
271 .ib_test = NULL,
272 .irq_set = &r100_irq_set, 217 .irq_set = &r100_irq_set,
273 .irq_process = &r100_irq_process, 218 .irq_process = &r100_irq_process,
274 .get_vblank_counter = &r100_get_vblank_counter, 219 .get_vblank_counter = &r100_get_vblank_counter,
@@ -307,27 +252,13 @@ static struct radeon_asic rs600_asic = {
307 .fini = &rs600_fini, 252 .fini = &rs600_fini,
308 .suspend = &rs600_suspend, 253 .suspend = &rs600_suspend,
309 .resume = &rs600_resume, 254 .resume = &rs600_resume,
310 .errata = NULL,
311 .vram_info = NULL,
312 .gpu_reset = &r300_gpu_reset, 255 .gpu_reset = &r300_gpu_reset,
313 .mc_init = NULL,
314 .mc_fini = NULL,
315 .wb_init = NULL,
316 .wb_fini = NULL,
317 .gart_init = NULL,
318 .gart_fini = NULL,
319 .gart_enable = NULL,
320 .gart_disable = NULL,
321 .gart_tlb_flush = &rs600_gart_tlb_flush, 256 .gart_tlb_flush = &rs600_gart_tlb_flush,
322 .gart_set_page = &rs600_gart_set_page, 257 .gart_set_page = &rs600_gart_set_page,
323 .cp_init = NULL,
324 .cp_fini = NULL,
325 .cp_disable = NULL,
326 .cp_commit = &r100_cp_commit, 258 .cp_commit = &r100_cp_commit,
327 .ring_start = &r300_ring_start, 259 .ring_start = &r300_ring_start,
328 .ring_test = &r100_ring_test, 260 .ring_test = &r100_ring_test,
329 .ring_ib_execute = &r100_ring_ib_execute, 261 .ring_ib_execute = &r100_ring_ib_execute,
330 .ib_test = NULL,
331 .irq_set = &rs600_irq_set, 262 .irq_set = &rs600_irq_set,
332 .irq_process = &rs600_irq_process, 263 .irq_process = &rs600_irq_process,
333 .get_vblank_counter = &rs600_get_vblank_counter, 264 .get_vblank_counter = &rs600_get_vblank_counter,
@@ -359,27 +290,13 @@ static struct radeon_asic rs690_asic = {
359 .fini = &rs690_fini, 290 .fini = &rs690_fini,
360 .suspend = &rs690_suspend, 291 .suspend = &rs690_suspend,
361 .resume = &rs690_resume, 292 .resume = &rs690_resume,
362 .errata = NULL,
363 .vram_info = NULL,
364 .gpu_reset = &r300_gpu_reset, 293 .gpu_reset = &r300_gpu_reset,
365 .mc_init = NULL,
366 .mc_fini = NULL,
367 .wb_init = NULL,
368 .wb_fini = NULL,
369 .gart_init = NULL,
370 .gart_fini = NULL,
371 .gart_enable = NULL,
372 .gart_disable = NULL,
373 .gart_tlb_flush = &rs400_gart_tlb_flush, 294 .gart_tlb_flush = &rs400_gart_tlb_flush,
374 .gart_set_page = &rs400_gart_set_page, 295 .gart_set_page = &rs400_gart_set_page,
375 .cp_init = NULL,
376 .cp_fini = NULL,
377 .cp_disable = NULL,
378 .cp_commit = &r100_cp_commit, 296 .cp_commit = &r100_cp_commit,
379 .ring_start = &r300_ring_start, 297 .ring_start = &r300_ring_start,
380 .ring_test = &r100_ring_test, 298 .ring_test = &r100_ring_test,
381 .ring_ib_execute = &r100_ring_ib_execute, 299 .ring_ib_execute = &r100_ring_ib_execute,
382 .ib_test = NULL,
383 .irq_set = &rs600_irq_set, 300 .irq_set = &rs600_irq_set,
384 .irq_process = &rs600_irq_process, 301 .irq_process = &rs600_irq_process,
385 .get_vblank_counter = &rs600_get_vblank_counter, 302 .get_vblank_counter = &rs600_get_vblank_counter,
@@ -417,27 +334,13 @@ static struct radeon_asic rv515_asic = {
417 .fini = &rv515_fini, 334 .fini = &rv515_fini,
418 .suspend = &rv515_suspend, 335 .suspend = &rv515_suspend,
419 .resume = &rv515_resume, 336 .resume = &rv515_resume,
420 .errata = NULL,
421 .vram_info = NULL,
422 .gpu_reset = &rv515_gpu_reset, 337 .gpu_reset = &rv515_gpu_reset,
423 .mc_init = NULL,
424 .mc_fini = NULL,
425 .wb_init = NULL,
426 .wb_fini = NULL,
427 .gart_init = &rv370_pcie_gart_init,
428 .gart_fini = &rv370_pcie_gart_fini,
429 .gart_enable = NULL,
430 .gart_disable = NULL,
431 .gart_tlb_flush = &rv370_pcie_gart_tlb_flush, 338 .gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
432 .gart_set_page = &rv370_pcie_gart_set_page, 339 .gart_set_page = &rv370_pcie_gart_set_page,
433 .cp_init = NULL,
434 .cp_fini = NULL,
435 .cp_disable = NULL,
436 .cp_commit = &r100_cp_commit, 340 .cp_commit = &r100_cp_commit,
437 .ring_start = &rv515_ring_start, 341 .ring_start = &rv515_ring_start,
438 .ring_test = &r100_ring_test, 342 .ring_test = &r100_ring_test,
439 .ring_ib_execute = &r100_ring_ib_execute, 343 .ring_ib_execute = &r100_ring_ib_execute,
440 .ib_test = NULL,
441 .irq_set = &rs600_irq_set, 344 .irq_set = &rs600_irq_set,
442 .irq_process = &rs600_irq_process, 345 .irq_process = &rs600_irq_process,
443 .get_vblank_counter = &rs600_get_vblank_counter, 346 .get_vblank_counter = &rs600_get_vblank_counter,
@@ -466,27 +369,13 @@ static struct radeon_asic r520_asic = {
466 .fini = &rv515_fini, 369 .fini = &rv515_fini,
467 .suspend = &rv515_suspend, 370 .suspend = &rv515_suspend,
468 .resume = &r520_resume, 371 .resume = &r520_resume,
469 .errata = NULL,
470 .vram_info = NULL,
471 .gpu_reset = &rv515_gpu_reset, 372 .gpu_reset = &rv515_gpu_reset,
472 .mc_init = NULL,
473 .mc_fini = NULL,
474 .wb_init = NULL,
475 .wb_fini = NULL,
476 .gart_init = NULL,
477 .gart_fini = NULL,
478 .gart_enable = NULL,
479 .gart_disable = NULL,
480 .gart_tlb_flush = &rv370_pcie_gart_tlb_flush, 373 .gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
481 .gart_set_page = &rv370_pcie_gart_set_page, 374 .gart_set_page = &rv370_pcie_gart_set_page,
482 .cp_init = NULL,
483 .cp_fini = NULL,
484 .cp_disable = NULL,
485 .cp_commit = &r100_cp_commit, 375 .cp_commit = &r100_cp_commit,
486 .ring_start = &rv515_ring_start, 376 .ring_start = &rv515_ring_start,
487 .ring_test = &r100_ring_test, 377 .ring_test = &r100_ring_test,
488 .ring_ib_execute = &r100_ring_ib_execute, 378 .ring_ib_execute = &r100_ring_ib_execute,
489 .ib_test = NULL,
490 .irq_set = &rs600_irq_set, 379 .irq_set = &rs600_irq_set,
491 .irq_process = &rs600_irq_process, 380 .irq_process = &rs600_irq_process,
492 .get_vblank_counter = &rs600_get_vblank_counter, 381 .get_vblank_counter = &rs600_get_vblank_counter,
@@ -533,36 +422,22 @@ int r600_set_surface_reg(struct radeon_device *rdev, int reg,
533 uint32_t offset, uint32_t obj_size); 422 uint32_t offset, uint32_t obj_size);
534int r600_clear_surface_reg(struct radeon_device *rdev, int reg); 423int r600_clear_surface_reg(struct radeon_device *rdev, int reg);
535void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 424void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
536int r600_ib_test(struct radeon_device *rdev);
537int r600_ring_test(struct radeon_device *rdev); 425int r600_ring_test(struct radeon_device *rdev);
538int r600_copy_blit(struct radeon_device *rdev, 426int r600_copy_blit(struct radeon_device *rdev,
539 uint64_t src_offset, uint64_t dst_offset, 427 uint64_t src_offset, uint64_t dst_offset,
540 unsigned num_pages, struct radeon_fence *fence); 428 unsigned num_pages, struct radeon_fence *fence);
541 429
542static struct radeon_asic r600_asic = { 430static struct radeon_asic r600_asic = {
543 .errata = NULL,
544 .init = &r600_init, 431 .init = &r600_init,
545 .fini = &r600_fini, 432 .fini = &r600_fini,
546 .suspend = &r600_suspend, 433 .suspend = &r600_suspend,
547 .resume = &r600_resume, 434 .resume = &r600_resume,
548 .cp_commit = &r600_cp_commit, 435 .cp_commit = &r600_cp_commit,
549 .vram_info = NULL,
550 .gpu_reset = &r600_gpu_reset, 436 .gpu_reset = &r600_gpu_reset,
551 .mc_init = NULL,
552 .mc_fini = NULL,
553 .wb_init = &r600_wb_init,
554 .wb_fini = &r600_wb_fini,
555 .gart_enable = NULL,
556 .gart_disable = NULL,
557 .gart_tlb_flush = &r600_pcie_gart_tlb_flush, 437 .gart_tlb_flush = &r600_pcie_gart_tlb_flush,
558 .gart_set_page = &rs600_gart_set_page, 438 .gart_set_page = &rs600_gart_set_page,
559 .cp_init = NULL,
560 .cp_fini = NULL,
561 .cp_disable = NULL,
562 .ring_start = NULL,
563 .ring_test = &r600_ring_test, 439 .ring_test = &r600_ring_test,
564 .ring_ib_execute = &r600_ring_ib_execute, 440 .ring_ib_execute = &r600_ring_ib_execute,
565 .ib_test = &r600_ib_test,
566 .irq_set = &r600_irq_set, 441 .irq_set = &r600_irq_set,
567 .irq_process = &r600_irq_process, 442 .irq_process = &r600_irq_process,
568 .fence_ring_emit = &r600_fence_ring_emit, 443 .fence_ring_emit = &r600_fence_ring_emit,
@@ -589,29 +464,16 @@ int rv770_resume(struct radeon_device *rdev);
589int rv770_gpu_reset(struct radeon_device *rdev); 464int rv770_gpu_reset(struct radeon_device *rdev);
590 465
591static struct radeon_asic rv770_asic = { 466static struct radeon_asic rv770_asic = {
592 .errata = NULL,
593 .init = &rv770_init, 467 .init = &rv770_init,
594 .fini = &rv770_fini, 468 .fini = &rv770_fini,
595 .suspend = &rv770_suspend, 469 .suspend = &rv770_suspend,
596 .resume = &rv770_resume, 470 .resume = &rv770_resume,
597 .cp_commit = &r600_cp_commit, 471 .cp_commit = &r600_cp_commit,
598 .vram_info = NULL,
599 .gpu_reset = &rv770_gpu_reset, 472 .gpu_reset = &rv770_gpu_reset,
600 .mc_init = NULL,
601 .mc_fini = NULL,
602 .wb_init = &r600_wb_init,
603 .wb_fini = &r600_wb_fini,
604 .gart_enable = NULL,
605 .gart_disable = NULL,
606 .gart_tlb_flush = &r600_pcie_gart_tlb_flush, 473 .gart_tlb_flush = &r600_pcie_gart_tlb_flush,
607 .gart_set_page = &rs600_gart_set_page, 474 .gart_set_page = &rs600_gart_set_page,
608 .cp_init = NULL,
609 .cp_fini = NULL,
610 .cp_disable = NULL,
611 .ring_start = NULL,
612 .ring_test = &r600_ring_test, 475 .ring_test = &r600_ring_test,
613 .ring_ib_execute = &r600_ring_ib_execute, 476 .ring_ib_execute = &r600_ring_ib_execute,
614 .ib_test = &r600_ib_test,
615 .irq_set = &r600_irq_set, 477 .irq_set = &r600_irq_set,
616 .irq_process = &r600_irq_process, 478 .irq_process = &r600_irq_process,
617 .fence_ring_emit = &r600_fence_ring_emit, 479 .fence_ring_emit = &r600_fence_ring_emit,
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-22 18:37:55 -0400