diff options
author | Alex Deucher <alexdeucher@gmail.com> | 2009-12-23 10:07:50 -0500 |
---|---|---|
committer | Dave Airlie <airlied@redhat.com> | 2010-02-08 18:32:26 -0500 |
commit | c836a4126768cd76af9ee33b3c11f57695d5fda6 (patch) | |
tree | 7f9eebbab1ae7d6956ca87c23e0933e3d1331f71 /drivers/gpu/drm/radeon/radeon_asic.h | |
parent | c913e23a145ae07b6f9f88aae8cd5ad06b5729ff (diff) |
drm/radeon/kms: add functions to get current pcie lanes
Currently unused.
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/radeon_asic.h')
-rw-r--r-- | drivers/gpu/drm/radeon/radeon_asic.h | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/radeon_asic.h b/drivers/gpu/drm/radeon/radeon_asic.h index 05ee1aeac3fd..d758b1ffb74c 100644 --- a/drivers/gpu/drm/radeon/radeon_asic.h +++ b/drivers/gpu/drm/radeon/radeon_asic.h | |||
@@ -108,6 +108,7 @@ static struct radeon_asic r100_asic = { | |||
108 | .set_engine_clock = &radeon_legacy_set_engine_clock, | 108 | .set_engine_clock = &radeon_legacy_set_engine_clock, |
109 | .get_memory_clock = &radeon_legacy_get_memory_clock, | 109 | .get_memory_clock = &radeon_legacy_get_memory_clock, |
110 | .set_memory_clock = NULL, | 110 | .set_memory_clock = NULL, |
111 | .get_pcie_lanes = NULL, | ||
111 | .set_pcie_lanes = NULL, | 112 | .set_pcie_lanes = NULL, |
112 | .set_clock_gating = &radeon_legacy_set_clock_gating, | 113 | .set_clock_gating = &radeon_legacy_set_clock_gating, |
113 | .set_surface_reg = r100_set_surface_reg, | 114 | .set_surface_reg = r100_set_surface_reg, |
@@ -138,6 +139,7 @@ extern int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t | |||
138 | extern uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg); | 139 | extern uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg); |
139 | extern void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); | 140 | extern void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); |
140 | extern void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes); | 141 | extern void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes); |
142 | extern int rv370_get_pcie_lanes(struct radeon_device *rdev); | ||
141 | extern int r300_copy_dma(struct radeon_device *rdev, | 143 | extern int r300_copy_dma(struct radeon_device *rdev, |
142 | uint64_t src_offset, | 144 | uint64_t src_offset, |
143 | uint64_t dst_offset, | 145 | uint64_t dst_offset, |
@@ -168,6 +170,7 @@ static struct radeon_asic r300_asic = { | |||
168 | .set_engine_clock = &radeon_legacy_set_engine_clock, | 170 | .set_engine_clock = &radeon_legacy_set_engine_clock, |
169 | .get_memory_clock = &radeon_legacy_get_memory_clock, | 171 | .get_memory_clock = &radeon_legacy_get_memory_clock, |
170 | .set_memory_clock = NULL, | 172 | .set_memory_clock = NULL, |
173 | .get_pcie_lanes = &rv370_get_pcie_lanes, | ||
171 | .set_pcie_lanes = &rv370_set_pcie_lanes, | 174 | .set_pcie_lanes = &rv370_set_pcie_lanes, |
172 | .set_clock_gating = &radeon_legacy_set_clock_gating, | 175 | .set_clock_gating = &radeon_legacy_set_clock_gating, |
173 | .set_surface_reg = r100_set_surface_reg, | 176 | .set_surface_reg = r100_set_surface_reg, |
@@ -212,6 +215,7 @@ static struct radeon_asic r420_asic = { | |||
212 | .set_engine_clock = &radeon_atom_set_engine_clock, | 215 | .set_engine_clock = &radeon_atom_set_engine_clock, |
213 | .get_memory_clock = &radeon_atom_get_memory_clock, | 216 | .get_memory_clock = &radeon_atom_get_memory_clock, |
214 | .set_memory_clock = &radeon_atom_set_memory_clock, | 217 | .set_memory_clock = &radeon_atom_set_memory_clock, |
218 | .get_pcie_lanes = &rv370_get_pcie_lanes, | ||
215 | .set_pcie_lanes = &rv370_set_pcie_lanes, | 219 | .set_pcie_lanes = &rv370_set_pcie_lanes, |
216 | .set_clock_gating = &radeon_atom_set_clock_gating, | 220 | .set_clock_gating = &radeon_atom_set_clock_gating, |
217 | .set_surface_reg = r100_set_surface_reg, | 221 | .set_surface_reg = r100_set_surface_reg, |
@@ -261,6 +265,7 @@ static struct radeon_asic rs400_asic = { | |||
261 | .set_engine_clock = &radeon_legacy_set_engine_clock, | 265 | .set_engine_clock = &radeon_legacy_set_engine_clock, |
262 | .get_memory_clock = &radeon_legacy_get_memory_clock, | 266 | .get_memory_clock = &radeon_legacy_get_memory_clock, |
263 | .set_memory_clock = NULL, | 267 | .set_memory_clock = NULL, |
268 | .get_pcie_lanes = NULL, | ||
264 | .set_pcie_lanes = NULL, | 269 | .set_pcie_lanes = NULL, |
265 | .set_clock_gating = &radeon_legacy_set_clock_gating, | 270 | .set_clock_gating = &radeon_legacy_set_clock_gating, |
266 | .set_surface_reg = r100_set_surface_reg, | 271 | .set_surface_reg = r100_set_surface_reg, |
@@ -320,6 +325,7 @@ static struct radeon_asic rs600_asic = { | |||
320 | .set_engine_clock = &radeon_atom_set_engine_clock, | 325 | .set_engine_clock = &radeon_atom_set_engine_clock, |
321 | .get_memory_clock = &radeon_atom_get_memory_clock, | 326 | .get_memory_clock = &radeon_atom_get_memory_clock, |
322 | .set_memory_clock = &radeon_atom_set_memory_clock, | 327 | .set_memory_clock = &radeon_atom_set_memory_clock, |
328 | .get_pcie_lanes = NULL, | ||
323 | .set_pcie_lanes = NULL, | 329 | .set_pcie_lanes = NULL, |
324 | .set_clock_gating = &radeon_atom_set_clock_gating, | 330 | .set_clock_gating = &radeon_atom_set_clock_gating, |
325 | .bandwidth_update = &rs600_bandwidth_update, | 331 | .bandwidth_update = &rs600_bandwidth_update, |
@@ -366,6 +372,7 @@ static struct radeon_asic rs690_asic = { | |||
366 | .set_engine_clock = &radeon_atom_set_engine_clock, | 372 | .set_engine_clock = &radeon_atom_set_engine_clock, |
367 | .get_memory_clock = &radeon_atom_get_memory_clock, | 373 | .get_memory_clock = &radeon_atom_get_memory_clock, |
368 | .set_memory_clock = &radeon_atom_set_memory_clock, | 374 | .set_memory_clock = &radeon_atom_set_memory_clock, |
375 | .get_pcie_lanes = NULL, | ||
369 | .set_pcie_lanes = NULL, | 376 | .set_pcie_lanes = NULL, |
370 | .set_clock_gating = &radeon_atom_set_clock_gating, | 377 | .set_clock_gating = &radeon_atom_set_clock_gating, |
371 | .set_surface_reg = r100_set_surface_reg, | 378 | .set_surface_reg = r100_set_surface_reg, |
@@ -418,6 +425,7 @@ static struct radeon_asic rv515_asic = { | |||
418 | .set_engine_clock = &radeon_atom_set_engine_clock, | 425 | .set_engine_clock = &radeon_atom_set_engine_clock, |
419 | .get_memory_clock = &radeon_atom_get_memory_clock, | 426 | .get_memory_clock = &radeon_atom_get_memory_clock, |
420 | .set_memory_clock = &radeon_atom_set_memory_clock, | 427 | .set_memory_clock = &radeon_atom_set_memory_clock, |
428 | .get_pcie_lanes = &rv370_get_pcie_lanes, | ||
421 | .set_pcie_lanes = &rv370_set_pcie_lanes, | 429 | .set_pcie_lanes = &rv370_set_pcie_lanes, |
422 | .set_clock_gating = &radeon_atom_set_clock_gating, | 430 | .set_clock_gating = &radeon_atom_set_clock_gating, |
423 | .set_surface_reg = r100_set_surface_reg, | 431 | .set_surface_reg = r100_set_surface_reg, |
@@ -461,6 +469,7 @@ static struct radeon_asic r520_asic = { | |||
461 | .set_engine_clock = &radeon_atom_set_engine_clock, | 469 | .set_engine_clock = &radeon_atom_set_engine_clock, |
462 | .get_memory_clock = &radeon_atom_get_memory_clock, | 470 | .get_memory_clock = &radeon_atom_get_memory_clock, |
463 | .set_memory_clock = &radeon_atom_set_memory_clock, | 471 | .set_memory_clock = &radeon_atom_set_memory_clock, |
472 | .get_pcie_lanes = &rv370_get_pcie_lanes, | ||
464 | .set_pcie_lanes = &rv370_set_pcie_lanes, | 473 | .set_pcie_lanes = &rv370_set_pcie_lanes, |
465 | .set_clock_gating = &radeon_atom_set_clock_gating, | 474 | .set_clock_gating = &radeon_atom_set_clock_gating, |
466 | .set_surface_reg = r100_set_surface_reg, | 475 | .set_surface_reg = r100_set_surface_reg, |
@@ -538,6 +547,7 @@ static struct radeon_asic r600_asic = { | |||
538 | .set_engine_clock = &radeon_atom_set_engine_clock, | 547 | .set_engine_clock = &radeon_atom_set_engine_clock, |
539 | .get_memory_clock = &radeon_atom_get_memory_clock, | 548 | .get_memory_clock = &radeon_atom_get_memory_clock, |
540 | .set_memory_clock = &radeon_atom_set_memory_clock, | 549 | .set_memory_clock = &radeon_atom_set_memory_clock, |
550 | .get_pcie_lanes = NULL, | ||
541 | .set_pcie_lanes = NULL, | 551 | .set_pcie_lanes = NULL, |
542 | .set_clock_gating = &radeon_atom_set_clock_gating, | 552 | .set_clock_gating = &radeon_atom_set_clock_gating, |
543 | .set_surface_reg = r600_set_surface_reg, | 553 | .set_surface_reg = r600_set_surface_reg, |
@@ -583,6 +593,7 @@ static struct radeon_asic rv770_asic = { | |||
583 | .set_engine_clock = &radeon_atom_set_engine_clock, | 593 | .set_engine_clock = &radeon_atom_set_engine_clock, |
584 | .get_memory_clock = &radeon_atom_get_memory_clock, | 594 | .get_memory_clock = &radeon_atom_get_memory_clock, |
585 | .set_memory_clock = &radeon_atom_set_memory_clock, | 595 | .set_memory_clock = &radeon_atom_set_memory_clock, |
596 | .get_pcie_lanes = NULL, | ||
586 | .set_pcie_lanes = NULL, | 597 | .set_pcie_lanes = NULL, |
587 | .set_clock_gating = &radeon_atom_set_clock_gating, | 598 | .set_clock_gating = &radeon_atom_set_clock_gating, |
588 | .set_surface_reg = r600_set_surface_reg, | 599 | .set_surface_reg = r600_set_surface_reg, |