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authorJerome Glisse <glisse@freedesktop.org>2009-06-17 07:28:30 -0400
committerDave Airlie <airlied@redhat.com>2009-06-18 19:32:27 -0400
commit068a117ca38f27c9641db7642f24fe9270d9424e (patch)
treee1038db118114aa777312a5eae70b512fa13617b /drivers/gpu/drm/radeon/radeon_asic.h
parent8b5c744485b75d940ccb1c83c9a358b20eb91346 (diff)
drm/radeon: command stream checker for r3xx-r5xx hardware
For security purpose we want to make sure the userspace process doesn't access memory beyond buffer it owns. To achieve this we need to check states the userspace program. For color buffer and zbuffer we check that the clipping register will discard access beyond buffers set as color or zbuffer. For vertex buffer we check that no vertex fetch will happen beyond buffer end. For texture we check various texture states (number of mipmap level, texture size, texture depth, ...) to compute the amount of memory the texture fetcher might access. The command stream checking impact the performances so far quick benchmark shows an average of 3% decrease in fps of various applications. It can be optimized a bit more by caching result of checking and thus avoid a full recheck if no states changed since last check. Note that this patch is still incomplete on checking side as it doesn't check 2d rendering states. Signed-off-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/radeon_asic.h')
-rw-r--r--drivers/gpu/drm/radeon/radeon_asic.h15
1 files changed, 13 insertions, 2 deletions
diff --git a/drivers/gpu/drm/radeon/radeon_asic.h b/drivers/gpu/drm/radeon/radeon_asic.h
index e57d8a784e9f..e2e567395df8 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.h
+++ b/drivers/gpu/drm/radeon/radeon_asic.h
@@ -41,6 +41,7 @@ void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
41/* 41/*
42 * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 42 * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
43 */ 43 */
44int r100_init(struct radeon_device *rdev);
44uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg); 45uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg);
45void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 46void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
46void r100_errata(struct radeon_device *rdev); 47void r100_errata(struct radeon_device *rdev);
@@ -72,6 +73,7 @@ int r100_copy_blit(struct radeon_device *rdev,
72 struct radeon_fence *fence); 73 struct radeon_fence *fence);
73 74
74static struct radeon_asic r100_asic = { 75static struct radeon_asic r100_asic = {
76 .init = &r100_init,
75 .errata = &r100_errata, 77 .errata = &r100_errata,
76 .vram_info = &r100_vram_info, 78 .vram_info = &r100_vram_info,
77 .gpu_reset = &r100_gpu_reset, 79 .gpu_reset = &r100_gpu_reset,
@@ -104,6 +106,7 @@ static struct radeon_asic r100_asic = {
104/* 106/*
105 * r300,r350,rv350,rv380 107 * r300,r350,rv350,rv380
106 */ 108 */
109int r300_init(struct radeon_device *rdev);
107void r300_errata(struct radeon_device *rdev); 110void r300_errata(struct radeon_device *rdev);
108void r300_vram_info(struct radeon_device *rdev); 111void r300_vram_info(struct radeon_device *rdev);
109int r300_gpu_reset(struct radeon_device *rdev); 112int r300_gpu_reset(struct radeon_device *rdev);
@@ -126,6 +129,7 @@ int r300_copy_dma(struct radeon_device *rdev,
126 unsigned num_pages, 129 unsigned num_pages,
127 struct radeon_fence *fence); 130 struct radeon_fence *fence);
128static struct radeon_asic r300_asic = { 131static struct radeon_asic r300_asic = {
132 .init = &r300_init,
129 .errata = &r300_errata, 133 .errata = &r300_errata,
130 .vram_info = &r300_vram_info, 134 .vram_info = &r300_vram_info,
131 .gpu_reset = &r300_gpu_reset, 135 .gpu_reset = &r300_gpu_reset,
@@ -162,6 +166,7 @@ void r420_vram_info(struct radeon_device *rdev);
162int r420_mc_init(struct radeon_device *rdev); 166int r420_mc_init(struct radeon_device *rdev);
163void r420_mc_fini(struct radeon_device *rdev); 167void r420_mc_fini(struct radeon_device *rdev);
164static struct radeon_asic r420_asic = { 168static struct radeon_asic r420_asic = {
169 .init = &r300_init,
165 .errata = &r420_errata, 170 .errata = &r420_errata,
166 .vram_info = &r420_vram_info, 171 .vram_info = &r420_vram_info,
167 .gpu_reset = &r300_gpu_reset, 172 .gpu_reset = &r300_gpu_reset,
@@ -205,6 +210,7 @@ int rs400_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
205uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg); 210uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg);
206void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 211void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
207static struct radeon_asic rs400_asic = { 212static struct radeon_asic rs400_asic = {
213 .init = &r300_init,
208 .errata = &rs400_errata, 214 .errata = &rs400_errata,
209 .vram_info = &rs400_vram_info, 215 .vram_info = &rs400_vram_info,
210 .gpu_reset = &r300_gpu_reset, 216 .gpu_reset = &r300_gpu_reset,
@@ -249,6 +255,7 @@ int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
249uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg); 255uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg);
250void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 256void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
251static struct radeon_asic rs600_asic = { 257static struct radeon_asic rs600_asic = {
258 .init = &r300_init,
252 .errata = &rs600_errata, 259 .errata = &rs600_errata,
253 .vram_info = &rs600_vram_info, 260 .vram_info = &rs600_vram_info,
254 .gpu_reset = &r300_gpu_reset, 261 .gpu_reset = &r300_gpu_reset,
@@ -288,6 +295,7 @@ void rs690_mc_fini(struct radeon_device *rdev);
288uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg); 295uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg);
289void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 296void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
290static struct radeon_asic rs690_asic = { 297static struct radeon_asic rs690_asic = {
298 .init = &r300_init,
291 .errata = &rs690_errata, 299 .errata = &rs690_errata,
292 .vram_info = &rs690_vram_info, 300 .vram_info = &rs690_vram_info,
293 .gpu_reset = &r300_gpu_reset, 301 .gpu_reset = &r300_gpu_reset,
@@ -320,6 +328,7 @@ static struct radeon_asic rs690_asic = {
320/* 328/*
321 * rv515 329 * rv515
322 */ 330 */
331int rv515_init(struct radeon_device *rdev);
323void rv515_errata(struct radeon_device *rdev); 332void rv515_errata(struct radeon_device *rdev);
324void rv515_vram_info(struct radeon_device *rdev); 333void rv515_vram_info(struct radeon_device *rdev);
325int rv515_gpu_reset(struct radeon_device *rdev); 334int rv515_gpu_reset(struct radeon_device *rdev);
@@ -331,6 +340,7 @@ void rv515_ring_start(struct radeon_device *rdev);
331uint32_t rv515_pcie_rreg(struct radeon_device *rdev, uint32_t reg); 340uint32_t rv515_pcie_rreg(struct radeon_device *rdev, uint32_t reg);
332void rv515_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 341void rv515_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
333static struct radeon_asic rv515_asic = { 342static struct radeon_asic rv515_asic = {
343 .init = &rv515_init,
334 .errata = &rv515_errata, 344 .errata = &rv515_errata,
335 .vram_info = &rv515_vram_info, 345 .vram_info = &rv515_vram_info,
336 .gpu_reset = &rv515_gpu_reset, 346 .gpu_reset = &rv515_gpu_reset,
@@ -349,7 +359,7 @@ static struct radeon_asic rv515_asic = {
349 .irq_set = &r100_irq_set, 359 .irq_set = &r100_irq_set,
350 .irq_process = &r100_irq_process, 360 .irq_process = &r100_irq_process,
351 .fence_ring_emit = &r300_fence_ring_emit, 361 .fence_ring_emit = &r300_fence_ring_emit,
352 .cs_parse = &r100_cs_parse, 362 .cs_parse = &r300_cs_parse,
353 .copy_blit = &r100_copy_blit, 363 .copy_blit = &r100_copy_blit,
354 .copy_dma = &r300_copy_dma, 364 .copy_dma = &r300_copy_dma,
355 .copy = &r100_copy_blit, 365 .copy = &r100_copy_blit,
@@ -368,6 +378,7 @@ void r520_vram_info(struct radeon_device *rdev);
368int r520_mc_init(struct radeon_device *rdev); 378int r520_mc_init(struct radeon_device *rdev);
369void r520_mc_fini(struct radeon_device *rdev); 379void r520_mc_fini(struct radeon_device *rdev);
370static struct radeon_asic r520_asic = { 380static struct radeon_asic r520_asic = {
381 .init = &rv515_init,
371 .errata = &r520_errata, 382 .errata = &r520_errata,
372 .vram_info = &r520_vram_info, 383 .vram_info = &r520_vram_info,
373 .gpu_reset = &rv515_gpu_reset, 384 .gpu_reset = &rv515_gpu_reset,
@@ -386,7 +397,7 @@ static struct radeon_asic r520_asic = {
386 .irq_set = &r100_irq_set, 397 .irq_set = &r100_irq_set,
387 .irq_process = &r100_irq_process, 398 .irq_process = &r100_irq_process,
388 .fence_ring_emit = &r300_fence_ring_emit, 399 .fence_ring_emit = &r300_fence_ring_emit,
389 .cs_parse = &r100_cs_parse, 400 .cs_parse = &r300_cs_parse,
390 .copy_blit = &r100_copy_blit, 401 .copy_blit = &r100_copy_blit,
391 .copy_dma = &r300_copy_dma, 402 .copy_dma = &r300_copy_dma,
392 .copy = &r100_copy_blit, 403 .copy = &r100_copy_blit,