diff options
author | Alex Deucher <alexander.deucher@amd.com> | 2012-02-23 17:53:45 -0500 |
---|---|---|
committer | Dave Airlie <airlied@redhat.com> | 2012-02-29 05:14:47 -0500 |
commit | f712812e1ba7f17a270f285c3e7e70c65186a8b4 (patch) | |
tree | 00b31997e1b369cca4dc7709b31a273fd9be3b3b /drivers/gpu/drm/radeon/radeon_asic.c | |
parent | dfb276f098e0e90319a346bae2f205f2690d6b42 (diff) |
drm/radeon/kms: make ring_start, ring_test, and ib_test per ring
Each ring type may need a different variant.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König<christian.koenig@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/radeon_asic.c')
-rw-r--r-- | drivers/gpu/drm/radeon/radeon_asic.c | 75 |
1 files changed, 48 insertions, 27 deletions
diff --git a/drivers/gpu/drm/radeon/radeon_asic.c b/drivers/gpu/drm/radeon/radeon_asic.c index a7b6c37d8fa4..85e13502e80f 100644 --- a/drivers/gpu/drm/radeon/radeon_asic.c +++ b/drivers/gpu/drm/radeon/radeon_asic.c | |||
@@ -138,14 +138,15 @@ static struct radeon_asic r100_asic = { | |||
138 | .asic_reset = &r100_asic_reset, | 138 | .asic_reset = &r100_asic_reset, |
139 | .gart_tlb_flush = &r100_pci_gart_tlb_flush, | 139 | .gart_tlb_flush = &r100_pci_gart_tlb_flush, |
140 | .gart_set_page = &r100_pci_gart_set_page, | 140 | .gart_set_page = &r100_pci_gart_set_page, |
141 | .ring_start = &r100_ring_start, | ||
142 | .ring_test = &r100_ring_test, | ||
143 | .ring = { | 141 | .ring = { |
144 | [RADEON_RING_TYPE_GFX_INDEX] = { | 142 | [RADEON_RING_TYPE_GFX_INDEX] = { |
145 | .ib_execute = &r100_ring_ib_execute, | 143 | .ib_execute = &r100_ring_ib_execute, |
146 | .emit_fence = &r100_fence_ring_emit, | 144 | .emit_fence = &r100_fence_ring_emit, |
147 | .emit_semaphore = &r100_semaphore_ring_emit, | 145 | .emit_semaphore = &r100_semaphore_ring_emit, |
148 | .cs_parse = &r100_cs_parse, | 146 | .cs_parse = &r100_cs_parse, |
147 | .ring_start = &r100_ring_start, | ||
148 | .ring_test = &r100_ring_test, | ||
149 | .ib_test = &r100_ib_test, | ||
149 | } | 150 | } |
150 | }, | 151 | }, |
151 | .irq = { | 152 | .irq = { |
@@ -205,14 +206,15 @@ static struct radeon_asic r200_asic = { | |||
205 | .asic_reset = &r100_asic_reset, | 206 | .asic_reset = &r100_asic_reset, |
206 | .gart_tlb_flush = &r100_pci_gart_tlb_flush, | 207 | .gart_tlb_flush = &r100_pci_gart_tlb_flush, |
207 | .gart_set_page = &r100_pci_gart_set_page, | 208 | .gart_set_page = &r100_pci_gart_set_page, |
208 | .ring_start = &r100_ring_start, | ||
209 | .ring_test = &r100_ring_test, | ||
210 | .ring = { | 209 | .ring = { |
211 | [RADEON_RING_TYPE_GFX_INDEX] = { | 210 | [RADEON_RING_TYPE_GFX_INDEX] = { |
212 | .ib_execute = &r100_ring_ib_execute, | 211 | .ib_execute = &r100_ring_ib_execute, |
213 | .emit_fence = &r100_fence_ring_emit, | 212 | .emit_fence = &r100_fence_ring_emit, |
214 | .emit_semaphore = &r100_semaphore_ring_emit, | 213 | .emit_semaphore = &r100_semaphore_ring_emit, |
215 | .cs_parse = &r100_cs_parse, | 214 | .cs_parse = &r100_cs_parse, |
215 | .ring_start = &r100_ring_start, | ||
216 | .ring_test = &r100_ring_test, | ||
217 | .ib_test = &r100_ib_test, | ||
216 | } | 218 | } |
217 | }, | 219 | }, |
218 | .irq = { | 220 | .irq = { |
@@ -271,14 +273,15 @@ static struct radeon_asic r300_asic = { | |||
271 | .asic_reset = &r300_asic_reset, | 273 | .asic_reset = &r300_asic_reset, |
272 | .gart_tlb_flush = &r100_pci_gart_tlb_flush, | 274 | .gart_tlb_flush = &r100_pci_gart_tlb_flush, |
273 | .gart_set_page = &r100_pci_gart_set_page, | 275 | .gart_set_page = &r100_pci_gart_set_page, |
274 | .ring_start = &r300_ring_start, | ||
275 | .ring_test = &r100_ring_test, | ||
276 | .ring = { | 276 | .ring = { |
277 | [RADEON_RING_TYPE_GFX_INDEX] = { | 277 | [RADEON_RING_TYPE_GFX_INDEX] = { |
278 | .ib_execute = &r100_ring_ib_execute, | 278 | .ib_execute = &r100_ring_ib_execute, |
279 | .emit_fence = &r300_fence_ring_emit, | 279 | .emit_fence = &r300_fence_ring_emit, |
280 | .emit_semaphore = &r100_semaphore_ring_emit, | 280 | .emit_semaphore = &r100_semaphore_ring_emit, |
281 | .cs_parse = &r300_cs_parse, | 281 | .cs_parse = &r300_cs_parse, |
282 | .ring_start = &r300_ring_start, | ||
283 | .ring_test = &r100_ring_test, | ||
284 | .ib_test = &r100_ib_test, | ||
282 | } | 285 | } |
283 | }, | 286 | }, |
284 | .irq = { | 287 | .irq = { |
@@ -338,14 +341,15 @@ static struct radeon_asic r300_asic_pcie = { | |||
338 | .asic_reset = &r300_asic_reset, | 341 | .asic_reset = &r300_asic_reset, |
339 | .gart_tlb_flush = &rv370_pcie_gart_tlb_flush, | 342 | .gart_tlb_flush = &rv370_pcie_gart_tlb_flush, |
340 | .gart_set_page = &rv370_pcie_gart_set_page, | 343 | .gart_set_page = &rv370_pcie_gart_set_page, |
341 | .ring_start = &r300_ring_start, | ||
342 | .ring_test = &r100_ring_test, | ||
343 | .ring = { | 344 | .ring = { |
344 | [RADEON_RING_TYPE_GFX_INDEX] = { | 345 | [RADEON_RING_TYPE_GFX_INDEX] = { |
345 | .ib_execute = &r100_ring_ib_execute, | 346 | .ib_execute = &r100_ring_ib_execute, |
346 | .emit_fence = &r300_fence_ring_emit, | 347 | .emit_fence = &r300_fence_ring_emit, |
347 | .emit_semaphore = &r100_semaphore_ring_emit, | 348 | .emit_semaphore = &r100_semaphore_ring_emit, |
348 | .cs_parse = &r300_cs_parse, | 349 | .cs_parse = &r300_cs_parse, |
350 | .ring_start = &r300_ring_start, | ||
351 | .ring_test = &r100_ring_test, | ||
352 | .ib_test = &r100_ib_test, | ||
349 | } | 353 | } |
350 | }, | 354 | }, |
351 | .irq = { | 355 | .irq = { |
@@ -404,14 +408,15 @@ static struct radeon_asic r420_asic = { | |||
404 | .asic_reset = &r300_asic_reset, | 408 | .asic_reset = &r300_asic_reset, |
405 | .gart_tlb_flush = &rv370_pcie_gart_tlb_flush, | 409 | .gart_tlb_flush = &rv370_pcie_gart_tlb_flush, |
406 | .gart_set_page = &rv370_pcie_gart_set_page, | 410 | .gart_set_page = &rv370_pcie_gart_set_page, |
407 | .ring_start = &r300_ring_start, | ||
408 | .ring_test = &r100_ring_test, | ||
409 | .ring = { | 411 | .ring = { |
410 | [RADEON_RING_TYPE_GFX_INDEX] = { | 412 | [RADEON_RING_TYPE_GFX_INDEX] = { |
411 | .ib_execute = &r100_ring_ib_execute, | 413 | .ib_execute = &r100_ring_ib_execute, |
412 | .emit_fence = &r300_fence_ring_emit, | 414 | .emit_fence = &r300_fence_ring_emit, |
413 | .emit_semaphore = &r100_semaphore_ring_emit, | 415 | .emit_semaphore = &r100_semaphore_ring_emit, |
414 | .cs_parse = &r300_cs_parse, | 416 | .cs_parse = &r300_cs_parse, |
417 | .ring_start = &r300_ring_start, | ||
418 | .ring_test = &r100_ring_test, | ||
419 | .ib_test = &r100_ib_test, | ||
415 | } | 420 | } |
416 | }, | 421 | }, |
417 | .irq = { | 422 | .irq = { |
@@ -471,14 +476,15 @@ static struct radeon_asic rs400_asic = { | |||
471 | .asic_reset = &r300_asic_reset, | 476 | .asic_reset = &r300_asic_reset, |
472 | .gart_tlb_flush = &rs400_gart_tlb_flush, | 477 | .gart_tlb_flush = &rs400_gart_tlb_flush, |
473 | .gart_set_page = &rs400_gart_set_page, | 478 | .gart_set_page = &rs400_gart_set_page, |
474 | .ring_start = &r300_ring_start, | ||
475 | .ring_test = &r100_ring_test, | ||
476 | .ring = { | 479 | .ring = { |
477 | [RADEON_RING_TYPE_GFX_INDEX] = { | 480 | [RADEON_RING_TYPE_GFX_INDEX] = { |
478 | .ib_execute = &r100_ring_ib_execute, | 481 | .ib_execute = &r100_ring_ib_execute, |
479 | .emit_fence = &r300_fence_ring_emit, | 482 | .emit_fence = &r300_fence_ring_emit, |
480 | .emit_semaphore = &r100_semaphore_ring_emit, | 483 | .emit_semaphore = &r100_semaphore_ring_emit, |
481 | .cs_parse = &r300_cs_parse, | 484 | .cs_parse = &r300_cs_parse, |
485 | .ring_start = &r300_ring_start, | ||
486 | .ring_test = &r100_ring_test, | ||
487 | .ib_test = &r100_ib_test, | ||
482 | } | 488 | } |
483 | }, | 489 | }, |
484 | .irq = { | 490 | .irq = { |
@@ -538,14 +544,15 @@ static struct radeon_asic rs600_asic = { | |||
538 | .asic_reset = &rs600_asic_reset, | 544 | .asic_reset = &rs600_asic_reset, |
539 | .gart_tlb_flush = &rs600_gart_tlb_flush, | 545 | .gart_tlb_flush = &rs600_gart_tlb_flush, |
540 | .gart_set_page = &rs600_gart_set_page, | 546 | .gart_set_page = &rs600_gart_set_page, |
541 | .ring_start = &r300_ring_start, | ||
542 | .ring_test = &r100_ring_test, | ||
543 | .ring = { | 547 | .ring = { |
544 | [RADEON_RING_TYPE_GFX_INDEX] = { | 548 | [RADEON_RING_TYPE_GFX_INDEX] = { |
545 | .ib_execute = &r100_ring_ib_execute, | 549 | .ib_execute = &r100_ring_ib_execute, |
546 | .emit_fence = &r300_fence_ring_emit, | 550 | .emit_fence = &r300_fence_ring_emit, |
547 | .emit_semaphore = &r100_semaphore_ring_emit, | 551 | .emit_semaphore = &r100_semaphore_ring_emit, |
548 | .cs_parse = &r300_cs_parse, | 552 | .cs_parse = &r300_cs_parse, |
553 | .ring_start = &r300_ring_start, | ||
554 | .ring_test = &r100_ring_test, | ||
555 | .ib_test = &r100_ib_test, | ||
549 | } | 556 | } |
550 | }, | 557 | }, |
551 | .irq = { | 558 | .irq = { |
@@ -605,14 +612,15 @@ static struct radeon_asic rs690_asic = { | |||
605 | .asic_reset = &rs600_asic_reset, | 612 | .asic_reset = &rs600_asic_reset, |
606 | .gart_tlb_flush = &rs400_gart_tlb_flush, | 613 | .gart_tlb_flush = &rs400_gart_tlb_flush, |
607 | .gart_set_page = &rs400_gart_set_page, | 614 | .gart_set_page = &rs400_gart_set_page, |
608 | .ring_start = &r300_ring_start, | ||
609 | .ring_test = &r100_ring_test, | ||
610 | .ring = { | 615 | .ring = { |
611 | [RADEON_RING_TYPE_GFX_INDEX] = { | 616 | [RADEON_RING_TYPE_GFX_INDEX] = { |
612 | .ib_execute = &r100_ring_ib_execute, | 617 | .ib_execute = &r100_ring_ib_execute, |
613 | .emit_fence = &r300_fence_ring_emit, | 618 | .emit_fence = &r300_fence_ring_emit, |
614 | .emit_semaphore = &r100_semaphore_ring_emit, | 619 | .emit_semaphore = &r100_semaphore_ring_emit, |
615 | .cs_parse = &r300_cs_parse, | 620 | .cs_parse = &r300_cs_parse, |
621 | .ring_start = &r300_ring_start, | ||
622 | .ring_test = &r100_ring_test, | ||
623 | .ib_test = &r100_ib_test, | ||
616 | } | 624 | } |
617 | }, | 625 | }, |
618 | .irq = { | 626 | .irq = { |
@@ -672,14 +680,15 @@ static struct radeon_asic rv515_asic = { | |||
672 | .asic_reset = &rs600_asic_reset, | 680 | .asic_reset = &rs600_asic_reset, |
673 | .gart_tlb_flush = &rv370_pcie_gart_tlb_flush, | 681 | .gart_tlb_flush = &rv370_pcie_gart_tlb_flush, |
674 | .gart_set_page = &rv370_pcie_gart_set_page, | 682 | .gart_set_page = &rv370_pcie_gart_set_page, |
675 | .ring_start = &rv515_ring_start, | ||
676 | .ring_test = &r100_ring_test, | ||
677 | .ring = { | 683 | .ring = { |
678 | [RADEON_RING_TYPE_GFX_INDEX] = { | 684 | [RADEON_RING_TYPE_GFX_INDEX] = { |
679 | .ib_execute = &r100_ring_ib_execute, | 685 | .ib_execute = &r100_ring_ib_execute, |
680 | .emit_fence = &r300_fence_ring_emit, | 686 | .emit_fence = &r300_fence_ring_emit, |
681 | .emit_semaphore = &r100_semaphore_ring_emit, | 687 | .emit_semaphore = &r100_semaphore_ring_emit, |
682 | .cs_parse = &r300_cs_parse, | 688 | .cs_parse = &r300_cs_parse, |
689 | .ring_start = &rv515_ring_start, | ||
690 | .ring_test = &r100_ring_test, | ||
691 | .ib_test = &r100_ib_test, | ||
683 | } | 692 | } |
684 | }, | 693 | }, |
685 | .irq = { | 694 | .irq = { |
@@ -739,14 +748,15 @@ static struct radeon_asic r520_asic = { | |||
739 | .asic_reset = &rs600_asic_reset, | 748 | .asic_reset = &rs600_asic_reset, |
740 | .gart_tlb_flush = &rv370_pcie_gart_tlb_flush, | 749 | .gart_tlb_flush = &rv370_pcie_gart_tlb_flush, |
741 | .gart_set_page = &rv370_pcie_gart_set_page, | 750 | .gart_set_page = &rv370_pcie_gart_set_page, |
742 | .ring_start = &rv515_ring_start, | ||
743 | .ring_test = &r100_ring_test, | ||
744 | .ring = { | 751 | .ring = { |
745 | [RADEON_RING_TYPE_GFX_INDEX] = { | 752 | [RADEON_RING_TYPE_GFX_INDEX] = { |
746 | .ib_execute = &r100_ring_ib_execute, | 753 | .ib_execute = &r100_ring_ib_execute, |
747 | .emit_fence = &r300_fence_ring_emit, | 754 | .emit_fence = &r300_fence_ring_emit, |
748 | .emit_semaphore = &r100_semaphore_ring_emit, | 755 | .emit_semaphore = &r100_semaphore_ring_emit, |
749 | .cs_parse = &r300_cs_parse, | 756 | .cs_parse = &r300_cs_parse, |
757 | .ring_start = &rv515_ring_start, | ||
758 | .ring_test = &r100_ring_test, | ||
759 | .ib_test = &r100_ib_test, | ||
750 | } | 760 | } |
751 | }, | 761 | }, |
752 | .irq = { | 762 | .irq = { |
@@ -806,13 +816,14 @@ static struct radeon_asic r600_asic = { | |||
806 | .asic_reset = &r600_asic_reset, | 816 | .asic_reset = &r600_asic_reset, |
807 | .gart_tlb_flush = &r600_pcie_gart_tlb_flush, | 817 | .gart_tlb_flush = &r600_pcie_gart_tlb_flush, |
808 | .gart_set_page = &rs600_gart_set_page, | 818 | .gart_set_page = &rs600_gart_set_page, |
809 | .ring_test = &r600_ring_test, | ||
810 | .ring = { | 819 | .ring = { |
811 | [RADEON_RING_TYPE_GFX_INDEX] = { | 820 | [RADEON_RING_TYPE_GFX_INDEX] = { |
812 | .ib_execute = &r600_ring_ib_execute, | 821 | .ib_execute = &r600_ring_ib_execute, |
813 | .emit_fence = &r600_fence_ring_emit, | 822 | .emit_fence = &r600_fence_ring_emit, |
814 | .emit_semaphore = &r600_semaphore_ring_emit, | 823 | .emit_semaphore = &r600_semaphore_ring_emit, |
815 | .cs_parse = &r600_cs_parse, | 824 | .cs_parse = &r600_cs_parse, |
825 | .ring_test = &r600_ring_test, | ||
826 | .ib_test = &r600_ib_test, | ||
816 | } | 827 | } |
817 | }, | 828 | }, |
818 | .irq = { | 829 | .irq = { |
@@ -872,13 +883,14 @@ static struct radeon_asic rs780_asic = { | |||
872 | .asic_reset = &r600_asic_reset, | 883 | .asic_reset = &r600_asic_reset, |
873 | .gart_tlb_flush = &r600_pcie_gart_tlb_flush, | 884 | .gart_tlb_flush = &r600_pcie_gart_tlb_flush, |
874 | .gart_set_page = &rs600_gart_set_page, | 885 | .gart_set_page = &rs600_gart_set_page, |
875 | .ring_test = &r600_ring_test, | ||
876 | .ring = { | 886 | .ring = { |
877 | [RADEON_RING_TYPE_GFX_INDEX] = { | 887 | [RADEON_RING_TYPE_GFX_INDEX] = { |
878 | .ib_execute = &r600_ring_ib_execute, | 888 | .ib_execute = &r600_ring_ib_execute, |
879 | .emit_fence = &r600_fence_ring_emit, | 889 | .emit_fence = &r600_fence_ring_emit, |
880 | .emit_semaphore = &r600_semaphore_ring_emit, | 890 | .emit_semaphore = &r600_semaphore_ring_emit, |
881 | .cs_parse = &r600_cs_parse, | 891 | .cs_parse = &r600_cs_parse, |
892 | .ring_test = &r600_ring_test, | ||
893 | .ib_test = &r600_ib_test, | ||
882 | } | 894 | } |
883 | }, | 895 | }, |
884 | .irq = { | 896 | .irq = { |
@@ -938,13 +950,14 @@ static struct radeon_asic rv770_asic = { | |||
938 | .vga_set_state = &r600_vga_set_state, | 950 | .vga_set_state = &r600_vga_set_state, |
939 | .gart_tlb_flush = &r600_pcie_gart_tlb_flush, | 951 | .gart_tlb_flush = &r600_pcie_gart_tlb_flush, |
940 | .gart_set_page = &rs600_gart_set_page, | 952 | .gart_set_page = &rs600_gart_set_page, |
941 | .ring_test = &r600_ring_test, | ||
942 | .ring = { | 953 | .ring = { |
943 | [RADEON_RING_TYPE_GFX_INDEX] = { | 954 | [RADEON_RING_TYPE_GFX_INDEX] = { |
944 | .ib_execute = &r600_ring_ib_execute, | 955 | .ib_execute = &r600_ring_ib_execute, |
945 | .emit_fence = &r600_fence_ring_emit, | 956 | .emit_fence = &r600_fence_ring_emit, |
946 | .emit_semaphore = &r600_semaphore_ring_emit, | 957 | .emit_semaphore = &r600_semaphore_ring_emit, |
947 | .cs_parse = &r600_cs_parse, | 958 | .cs_parse = &r600_cs_parse, |
959 | .ring_test = &r600_ring_test, | ||
960 | .ib_test = &r600_ib_test, | ||
948 | } | 961 | } |
949 | }, | 962 | }, |
950 | .irq = { | 963 | .irq = { |
@@ -1004,13 +1017,14 @@ static struct radeon_asic evergreen_asic = { | |||
1004 | .vga_set_state = &r600_vga_set_state, | 1017 | .vga_set_state = &r600_vga_set_state, |
1005 | .gart_tlb_flush = &evergreen_pcie_gart_tlb_flush, | 1018 | .gart_tlb_flush = &evergreen_pcie_gart_tlb_flush, |
1006 | .gart_set_page = &rs600_gart_set_page, | 1019 | .gart_set_page = &rs600_gart_set_page, |
1007 | .ring_test = &r600_ring_test, | ||
1008 | .ring = { | 1020 | .ring = { |
1009 | [RADEON_RING_TYPE_GFX_INDEX] = { | 1021 | [RADEON_RING_TYPE_GFX_INDEX] = { |
1010 | .ib_execute = &evergreen_ring_ib_execute, | 1022 | .ib_execute = &evergreen_ring_ib_execute, |
1011 | .emit_fence = &r600_fence_ring_emit, | 1023 | .emit_fence = &r600_fence_ring_emit, |
1012 | .emit_semaphore = &r600_semaphore_ring_emit, | 1024 | .emit_semaphore = &r600_semaphore_ring_emit, |
1013 | .cs_parse = &evergreen_cs_parse, | 1025 | .cs_parse = &evergreen_cs_parse, |
1026 | .ring_test = &r600_ring_test, | ||
1027 | .ib_test = &r600_ib_test, | ||
1014 | } | 1028 | } |
1015 | }, | 1029 | }, |
1016 | .irq = { | 1030 | .irq = { |
@@ -1070,13 +1084,14 @@ static struct radeon_asic sumo_asic = { | |||
1070 | .vga_set_state = &r600_vga_set_state, | 1084 | .vga_set_state = &r600_vga_set_state, |
1071 | .gart_tlb_flush = &evergreen_pcie_gart_tlb_flush, | 1085 | .gart_tlb_flush = &evergreen_pcie_gart_tlb_flush, |
1072 | .gart_set_page = &rs600_gart_set_page, | 1086 | .gart_set_page = &rs600_gart_set_page, |
1073 | .ring_test = &r600_ring_test, | ||
1074 | .ring = { | 1087 | .ring = { |
1075 | [RADEON_RING_TYPE_GFX_INDEX] = { | 1088 | [RADEON_RING_TYPE_GFX_INDEX] = { |
1076 | .ib_execute = &evergreen_ring_ib_execute, | 1089 | .ib_execute = &evergreen_ring_ib_execute, |
1077 | .emit_fence = &r600_fence_ring_emit, | 1090 | .emit_fence = &r600_fence_ring_emit, |
1078 | .emit_semaphore = &r600_semaphore_ring_emit, | 1091 | .emit_semaphore = &r600_semaphore_ring_emit, |
1079 | .cs_parse = &evergreen_cs_parse, | 1092 | .cs_parse = &evergreen_cs_parse, |
1093 | .ring_test = &r600_ring_test, | ||
1094 | .ib_test = &r600_ib_test, | ||
1080 | }, | 1095 | }, |
1081 | }, | 1096 | }, |
1082 | .irq = { | 1097 | .irq = { |
@@ -1136,13 +1151,14 @@ static struct radeon_asic btc_asic = { | |||
1136 | .vga_set_state = &r600_vga_set_state, | 1151 | .vga_set_state = &r600_vga_set_state, |
1137 | .gart_tlb_flush = &evergreen_pcie_gart_tlb_flush, | 1152 | .gart_tlb_flush = &evergreen_pcie_gart_tlb_flush, |
1138 | .gart_set_page = &rs600_gart_set_page, | 1153 | .gart_set_page = &rs600_gart_set_page, |
1139 | .ring_test = &r600_ring_test, | ||
1140 | .ring = { | 1154 | .ring = { |
1141 | [RADEON_RING_TYPE_GFX_INDEX] = { | 1155 | [RADEON_RING_TYPE_GFX_INDEX] = { |
1142 | .ib_execute = &evergreen_ring_ib_execute, | 1156 | .ib_execute = &evergreen_ring_ib_execute, |
1143 | .emit_fence = &r600_fence_ring_emit, | 1157 | .emit_fence = &r600_fence_ring_emit, |
1144 | .emit_semaphore = &r600_semaphore_ring_emit, | 1158 | .emit_semaphore = &r600_semaphore_ring_emit, |
1145 | .cs_parse = &evergreen_cs_parse, | 1159 | .cs_parse = &evergreen_cs_parse, |
1160 | .ring_test = &r600_ring_test, | ||
1161 | .ib_test = &r600_ib_test, | ||
1146 | } | 1162 | } |
1147 | }, | 1163 | }, |
1148 | .irq = { | 1164 | .irq = { |
@@ -1212,7 +1228,6 @@ static struct radeon_asic cayman_asic = { | |||
1212 | .vga_set_state = &r600_vga_set_state, | 1228 | .vga_set_state = &r600_vga_set_state, |
1213 | .gart_tlb_flush = &cayman_pcie_gart_tlb_flush, | 1229 | .gart_tlb_flush = &cayman_pcie_gart_tlb_flush, |
1214 | .gart_set_page = &rs600_gart_set_page, | 1230 | .gart_set_page = &rs600_gart_set_page, |
1215 | .ring_test = &r600_ring_test, | ||
1216 | .ring = { | 1231 | .ring = { |
1217 | [RADEON_RING_TYPE_GFX_INDEX] = { | 1232 | [RADEON_RING_TYPE_GFX_INDEX] = { |
1218 | .ib_execute = &cayman_ring_ib_execute, | 1233 | .ib_execute = &cayman_ring_ib_execute, |
@@ -1220,6 +1235,8 @@ static struct radeon_asic cayman_asic = { | |||
1220 | .emit_fence = &cayman_fence_ring_emit, | 1235 | .emit_fence = &cayman_fence_ring_emit, |
1221 | .emit_semaphore = &r600_semaphore_ring_emit, | 1236 | .emit_semaphore = &r600_semaphore_ring_emit, |
1222 | .cs_parse = &evergreen_cs_parse, | 1237 | .cs_parse = &evergreen_cs_parse, |
1238 | .ring_test = &r600_ring_test, | ||
1239 | .ib_test = &r600_ib_test, | ||
1223 | }, | 1240 | }, |
1224 | [CAYMAN_RING_TYPE_CP1_INDEX] = { | 1241 | [CAYMAN_RING_TYPE_CP1_INDEX] = { |
1225 | .ib_execute = &cayman_ring_ib_execute, | 1242 | .ib_execute = &cayman_ring_ib_execute, |
@@ -1227,6 +1244,8 @@ static struct radeon_asic cayman_asic = { | |||
1227 | .emit_fence = &cayman_fence_ring_emit, | 1244 | .emit_fence = &cayman_fence_ring_emit, |
1228 | .emit_semaphore = &r600_semaphore_ring_emit, | 1245 | .emit_semaphore = &r600_semaphore_ring_emit, |
1229 | .cs_parse = &evergreen_cs_parse, | 1246 | .cs_parse = &evergreen_cs_parse, |
1247 | .ring_test = &r600_ring_test, | ||
1248 | .ib_test = &r600_ib_test, | ||
1230 | }, | 1249 | }, |
1231 | [CAYMAN_RING_TYPE_CP2_INDEX] = { | 1250 | [CAYMAN_RING_TYPE_CP2_INDEX] = { |
1232 | .ib_execute = &cayman_ring_ib_execute, | 1251 | .ib_execute = &cayman_ring_ib_execute, |
@@ -1234,6 +1253,8 @@ static struct radeon_asic cayman_asic = { | |||
1234 | .emit_fence = &cayman_fence_ring_emit, | 1253 | .emit_fence = &cayman_fence_ring_emit, |
1235 | .emit_semaphore = &r600_semaphore_ring_emit, | 1254 | .emit_semaphore = &r600_semaphore_ring_emit, |
1236 | .cs_parse = &evergreen_cs_parse, | 1255 | .cs_parse = &evergreen_cs_parse, |
1256 | .ring_test = &r600_ring_test, | ||
1257 | .ib_test = &r600_ib_test, | ||
1237 | } | 1258 | } |
1238 | }, | 1259 | }, |
1239 | .irq = { | 1260 | .irq = { |