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authorChristian König <deathsimple@vodafone.de>2011-10-19 13:02:21 -0400
committerDave Airlie <airlied@redhat.com>2011-12-20 14:50:29 -0500
commit4c87bc268d764cf8846d20ea54b355d1e87507c9 (patch)
treeca037ba8ed18772c66ec00a0e433055775158e87 /drivers/gpu/drm/radeon/radeon_asic.c
parent60a7e3964db8cd698696b27f3c720365c374905a (diff)
drm/radeon: make some asic pointers per ring
Emitting fences, semaphores and ib works differently on different ring, so its is easier to maintain separate functions for each ring. Signed-off-by: Christian König <deathsimple@vodafone.de> Reviewed-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/radeon_asic.c')
-rw-r--r--drivers/gpu/drm/radeon/radeon_asic.c180
1 files changed, 129 insertions, 51 deletions
diff --git a/drivers/gpu/drm/radeon/radeon_asic.c b/drivers/gpu/drm/radeon/radeon_asic.c
index 1b208ed814a2..558933c759cb 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.c
+++ b/drivers/gpu/drm/radeon/radeon_asic.c
@@ -140,12 +140,16 @@ static struct radeon_asic r100_asic = {
140 .gart_set_page = &r100_pci_gart_set_page, 140 .gart_set_page = &r100_pci_gart_set_page,
141 .ring_start = &r100_ring_start, 141 .ring_start = &r100_ring_start,
142 .ring_test = &r100_ring_test, 142 .ring_test = &r100_ring_test,
143 .ring_ib_execute = &r100_ring_ib_execute, 143 .ring = {
144 [RADEON_RING_TYPE_GFX_INDEX] = {
145 .ib_execute = &r100_ring_ib_execute,
146 .emit_fence = &r100_fence_ring_emit,
147 .emit_semaphore = &r100_semaphore_ring_emit,
148 }
149 },
144 .irq_set = &r100_irq_set, 150 .irq_set = &r100_irq_set,
145 .irq_process = &r100_irq_process, 151 .irq_process = &r100_irq_process,
146 .get_vblank_counter = &r100_get_vblank_counter, 152 .get_vblank_counter = &r100_get_vblank_counter,
147 .fence_ring_emit = &r100_fence_ring_emit,
148 .semaphore_ring_emit = &r100_semaphore_ring_emit,
149 .cs_parse = &r100_cs_parse, 153 .cs_parse = &r100_cs_parse,
150 .copy_blit = &r100_copy_blit, 154 .copy_blit = &r100_copy_blit,
151 .copy_dma = NULL, 155 .copy_dma = NULL,
@@ -188,12 +192,16 @@ static struct radeon_asic r200_asic = {
188 .gart_set_page = &r100_pci_gart_set_page, 192 .gart_set_page = &r100_pci_gart_set_page,
189 .ring_start = &r100_ring_start, 193 .ring_start = &r100_ring_start,
190 .ring_test = &r100_ring_test, 194 .ring_test = &r100_ring_test,
191 .ring_ib_execute = &r100_ring_ib_execute, 195 .ring = {
196 [RADEON_RING_TYPE_GFX_INDEX] = {
197 .ib_execute = &r100_ring_ib_execute,
198 .emit_fence = &r100_fence_ring_emit,
199 .emit_semaphore = &r100_semaphore_ring_emit,
200 }
201 },
192 .irq_set = &r100_irq_set, 202 .irq_set = &r100_irq_set,
193 .irq_process = &r100_irq_process, 203 .irq_process = &r100_irq_process,
194 .get_vblank_counter = &r100_get_vblank_counter, 204 .get_vblank_counter = &r100_get_vblank_counter,
195 .fence_ring_emit = &r100_fence_ring_emit,
196 .semaphore_ring_emit = &r100_semaphore_ring_emit,
197 .cs_parse = &r100_cs_parse, 205 .cs_parse = &r100_cs_parse,
198 .copy_blit = &r100_copy_blit, 206 .copy_blit = &r100_copy_blit,
199 .copy_dma = &r200_copy_dma, 207 .copy_dma = &r200_copy_dma,
@@ -235,12 +243,16 @@ static struct radeon_asic r300_asic = {
235 .gart_set_page = &r100_pci_gart_set_page, 243 .gart_set_page = &r100_pci_gart_set_page,
236 .ring_start = &r300_ring_start, 244 .ring_start = &r300_ring_start,
237 .ring_test = &r100_ring_test, 245 .ring_test = &r100_ring_test,
238 .ring_ib_execute = &r100_ring_ib_execute, 246 .ring = {
247 [RADEON_RING_TYPE_GFX_INDEX] = {
248 .ib_execute = &r100_ring_ib_execute,
249 .emit_fence = &r300_fence_ring_emit,
250 .emit_semaphore = &r100_semaphore_ring_emit,
251 }
252 },
239 .irq_set = &r100_irq_set, 253 .irq_set = &r100_irq_set,
240 .irq_process = &r100_irq_process, 254 .irq_process = &r100_irq_process,
241 .get_vblank_counter = &r100_get_vblank_counter, 255 .get_vblank_counter = &r100_get_vblank_counter,
242 .fence_ring_emit = &r300_fence_ring_emit,
243 .semaphore_ring_emit = &r100_semaphore_ring_emit,
244 .cs_parse = &r300_cs_parse, 256 .cs_parse = &r300_cs_parse,
245 .copy_blit = &r100_copy_blit, 257 .copy_blit = &r100_copy_blit,
246 .copy_dma = &r200_copy_dma, 258 .copy_dma = &r200_copy_dma,
@@ -283,12 +295,16 @@ static struct radeon_asic r300_asic_pcie = {
283 .gart_set_page = &rv370_pcie_gart_set_page, 295 .gart_set_page = &rv370_pcie_gart_set_page,
284 .ring_start = &r300_ring_start, 296 .ring_start = &r300_ring_start,
285 .ring_test = &r100_ring_test, 297 .ring_test = &r100_ring_test,
286 .ring_ib_execute = &r100_ring_ib_execute, 298 .ring = {
299 [RADEON_RING_TYPE_GFX_INDEX] = {
300 .ib_execute = &r100_ring_ib_execute,
301 .emit_fence = &r300_fence_ring_emit,
302 .emit_semaphore = &r100_semaphore_ring_emit,
303 }
304 },
287 .irq_set = &r100_irq_set, 305 .irq_set = &r100_irq_set,
288 .irq_process = &r100_irq_process, 306 .irq_process = &r100_irq_process,
289 .get_vblank_counter = &r100_get_vblank_counter, 307 .get_vblank_counter = &r100_get_vblank_counter,
290 .fence_ring_emit = &r300_fence_ring_emit,
291 .semaphore_ring_emit = &r100_semaphore_ring_emit,
292 .cs_parse = &r300_cs_parse, 308 .cs_parse = &r300_cs_parse,
293 .copy_blit = &r100_copy_blit, 309 .copy_blit = &r100_copy_blit,
294 .copy_dma = &r200_copy_dma, 310 .copy_dma = &r200_copy_dma,
@@ -330,12 +346,16 @@ static struct radeon_asic r420_asic = {
330 .gart_set_page = &rv370_pcie_gart_set_page, 346 .gart_set_page = &rv370_pcie_gart_set_page,
331 .ring_start = &r300_ring_start, 347 .ring_start = &r300_ring_start,
332 .ring_test = &r100_ring_test, 348 .ring_test = &r100_ring_test,
333 .ring_ib_execute = &r100_ring_ib_execute, 349 .ring = {
350 [RADEON_RING_TYPE_GFX_INDEX] = {
351 .ib_execute = &r100_ring_ib_execute,
352 .emit_fence = &r300_fence_ring_emit,
353 .emit_semaphore = &r100_semaphore_ring_emit,
354 }
355 },
334 .irq_set = &r100_irq_set, 356 .irq_set = &r100_irq_set,
335 .irq_process = &r100_irq_process, 357 .irq_process = &r100_irq_process,
336 .get_vblank_counter = &r100_get_vblank_counter, 358 .get_vblank_counter = &r100_get_vblank_counter,
337 .fence_ring_emit = &r300_fence_ring_emit,
338 .semaphore_ring_emit = &r100_semaphore_ring_emit,
339 .cs_parse = &r300_cs_parse, 359 .cs_parse = &r300_cs_parse,
340 .copy_blit = &r100_copy_blit, 360 .copy_blit = &r100_copy_blit,
341 .copy_dma = &r200_copy_dma, 361 .copy_dma = &r200_copy_dma,
@@ -378,12 +398,16 @@ static struct radeon_asic rs400_asic = {
378 .gart_set_page = &rs400_gart_set_page, 398 .gart_set_page = &rs400_gart_set_page,
379 .ring_start = &r300_ring_start, 399 .ring_start = &r300_ring_start,
380 .ring_test = &r100_ring_test, 400 .ring_test = &r100_ring_test,
381 .ring_ib_execute = &r100_ring_ib_execute, 401 .ring = {
402 [RADEON_RING_TYPE_GFX_INDEX] = {
403 .ib_execute = &r100_ring_ib_execute,
404 .emit_fence = &r300_fence_ring_emit,
405 .emit_semaphore = &r100_semaphore_ring_emit,
406 }
407 },
382 .irq_set = &r100_irq_set, 408 .irq_set = &r100_irq_set,
383 .irq_process = &r100_irq_process, 409 .irq_process = &r100_irq_process,
384 .get_vblank_counter = &r100_get_vblank_counter, 410 .get_vblank_counter = &r100_get_vblank_counter,
385 .fence_ring_emit = &r300_fence_ring_emit,
386 .semaphore_ring_emit = &r100_semaphore_ring_emit,
387 .cs_parse = &r300_cs_parse, 411 .cs_parse = &r300_cs_parse,
388 .copy_blit = &r100_copy_blit, 412 .copy_blit = &r100_copy_blit,
389 .copy_dma = &r200_copy_dma, 413 .copy_dma = &r200_copy_dma,
@@ -426,12 +450,16 @@ static struct radeon_asic rs600_asic = {
426 .gart_set_page = &rs600_gart_set_page, 450 .gart_set_page = &rs600_gart_set_page,
427 .ring_start = &r300_ring_start, 451 .ring_start = &r300_ring_start,
428 .ring_test = &r100_ring_test, 452 .ring_test = &r100_ring_test,
429 .ring_ib_execute = &r100_ring_ib_execute, 453 .ring = {
454 [RADEON_RING_TYPE_GFX_INDEX] = {
455 .ib_execute = &r100_ring_ib_execute,
456 .emit_fence = &r300_fence_ring_emit,
457 .emit_semaphore = &r100_semaphore_ring_emit,
458 }
459 },
430 .irq_set = &rs600_irq_set, 460 .irq_set = &rs600_irq_set,
431 .irq_process = &rs600_irq_process, 461 .irq_process = &rs600_irq_process,
432 .get_vblank_counter = &rs600_get_vblank_counter, 462 .get_vblank_counter = &rs600_get_vblank_counter,
433 .fence_ring_emit = &r300_fence_ring_emit,
434 .semaphore_ring_emit = &r100_semaphore_ring_emit,
435 .cs_parse = &r300_cs_parse, 463 .cs_parse = &r300_cs_parse,
436 .copy_blit = &r100_copy_blit, 464 .copy_blit = &r100_copy_blit,
437 .copy_dma = &r200_copy_dma, 465 .copy_dma = &r200_copy_dma,
@@ -474,12 +502,16 @@ static struct radeon_asic rs690_asic = {
474 .gart_set_page = &rs400_gart_set_page, 502 .gart_set_page = &rs400_gart_set_page,
475 .ring_start = &r300_ring_start, 503 .ring_start = &r300_ring_start,
476 .ring_test = &r100_ring_test, 504 .ring_test = &r100_ring_test,
477 .ring_ib_execute = &r100_ring_ib_execute, 505 .ring = {
506 [RADEON_RING_TYPE_GFX_INDEX] = {
507 .ib_execute = &r100_ring_ib_execute,
508 .emit_fence = &r300_fence_ring_emit,
509 .emit_semaphore = &r100_semaphore_ring_emit,
510 }
511 },
478 .irq_set = &rs600_irq_set, 512 .irq_set = &rs600_irq_set,
479 .irq_process = &rs600_irq_process, 513 .irq_process = &rs600_irq_process,
480 .get_vblank_counter = &rs600_get_vblank_counter, 514 .get_vblank_counter = &rs600_get_vblank_counter,
481 .fence_ring_emit = &r300_fence_ring_emit,
482 .semaphore_ring_emit = &r100_semaphore_ring_emit,
483 .cs_parse = &r300_cs_parse, 515 .cs_parse = &r300_cs_parse,
484 .copy_blit = &r100_copy_blit, 516 .copy_blit = &r100_copy_blit,
485 .copy_dma = &r200_copy_dma, 517 .copy_dma = &r200_copy_dma,
@@ -522,12 +554,16 @@ static struct radeon_asic rv515_asic = {
522 .gart_set_page = &rv370_pcie_gart_set_page, 554 .gart_set_page = &rv370_pcie_gart_set_page,
523 .ring_start = &rv515_ring_start, 555 .ring_start = &rv515_ring_start,
524 .ring_test = &r100_ring_test, 556 .ring_test = &r100_ring_test,
525 .ring_ib_execute = &r100_ring_ib_execute, 557 .ring = {
558 [RADEON_RING_TYPE_GFX_INDEX] = {
559 .ib_execute = &r100_ring_ib_execute,
560 .emit_fence = &r300_fence_ring_emit,
561 .emit_semaphore = &r100_semaphore_ring_emit,
562 }
563 },
526 .irq_set = &rs600_irq_set, 564 .irq_set = &rs600_irq_set,
527 .irq_process = &rs600_irq_process, 565 .irq_process = &rs600_irq_process,
528 .get_vblank_counter = &rs600_get_vblank_counter, 566 .get_vblank_counter = &rs600_get_vblank_counter,
529 .fence_ring_emit = &r300_fence_ring_emit,
530 .semaphore_ring_emit = &r100_semaphore_ring_emit,
531 .cs_parse = &r300_cs_parse, 567 .cs_parse = &r300_cs_parse,
532 .copy_blit = &r100_copy_blit, 568 .copy_blit = &r100_copy_blit,
533 .copy_dma = &r200_copy_dma, 569 .copy_dma = &r200_copy_dma,
@@ -570,12 +606,16 @@ static struct radeon_asic r520_asic = {
570 .gart_set_page = &rv370_pcie_gart_set_page, 606 .gart_set_page = &rv370_pcie_gart_set_page,
571 .ring_start = &rv515_ring_start, 607 .ring_start = &rv515_ring_start,
572 .ring_test = &r100_ring_test, 608 .ring_test = &r100_ring_test,
573 .ring_ib_execute = &r100_ring_ib_execute, 609 .ring = {
610 [RADEON_RING_TYPE_GFX_INDEX] = {
611 .ib_execute = &r100_ring_ib_execute,
612 .emit_fence = &r300_fence_ring_emit,
613 .emit_semaphore = &r100_semaphore_ring_emit,
614 }
615 },
574 .irq_set = &rs600_irq_set, 616 .irq_set = &rs600_irq_set,
575 .irq_process = &rs600_irq_process, 617 .irq_process = &rs600_irq_process,
576 .get_vblank_counter = &rs600_get_vblank_counter, 618 .get_vblank_counter = &rs600_get_vblank_counter,
577 .fence_ring_emit = &r300_fence_ring_emit,
578 .semaphore_ring_emit = &r100_semaphore_ring_emit,
579 .cs_parse = &r300_cs_parse, 619 .cs_parse = &r300_cs_parse,
580 .copy_blit = &r100_copy_blit, 620 .copy_blit = &r100_copy_blit,
581 .copy_dma = &r200_copy_dma, 621 .copy_dma = &r200_copy_dma,
@@ -617,12 +657,16 @@ static struct radeon_asic r600_asic = {
617 .gart_tlb_flush = &r600_pcie_gart_tlb_flush, 657 .gart_tlb_flush = &r600_pcie_gart_tlb_flush,
618 .gart_set_page = &rs600_gart_set_page, 658 .gart_set_page = &rs600_gart_set_page,
619 .ring_test = &r600_ring_test, 659 .ring_test = &r600_ring_test,
620 .ring_ib_execute = &r600_ring_ib_execute, 660 .ring = {
661 [RADEON_RING_TYPE_GFX_INDEX] = {
662 .ib_execute = &r600_ring_ib_execute,
663 .emit_fence = &r600_fence_ring_emit,
664 .emit_semaphore = &r600_semaphore_ring_emit,
665 }
666 },
621 .irq_set = &r600_irq_set, 667 .irq_set = &r600_irq_set,
622 .irq_process = &r600_irq_process, 668 .irq_process = &r600_irq_process,
623 .get_vblank_counter = &rs600_get_vblank_counter, 669 .get_vblank_counter = &rs600_get_vblank_counter,
624 .fence_ring_emit = &r600_fence_ring_emit,
625 .semaphore_ring_emit = &r600_semaphore_ring_emit,
626 .cs_parse = &r600_cs_parse, 670 .cs_parse = &r600_cs_parse,
627 .copy_blit = &r600_copy_blit, 671 .copy_blit = &r600_copy_blit,
628 .copy_dma = NULL, 672 .copy_dma = NULL,
@@ -664,12 +708,16 @@ static struct radeon_asic rs780_asic = {
664 .gart_tlb_flush = &r600_pcie_gart_tlb_flush, 708 .gart_tlb_flush = &r600_pcie_gart_tlb_flush,
665 .gart_set_page = &rs600_gart_set_page, 709 .gart_set_page = &rs600_gart_set_page,
666 .ring_test = &r600_ring_test, 710 .ring_test = &r600_ring_test,
667 .ring_ib_execute = &r600_ring_ib_execute, 711 .ring = {
712 [RADEON_RING_TYPE_GFX_INDEX] = {
713 .ib_execute = &r600_ring_ib_execute,
714 .emit_fence = &r600_fence_ring_emit,
715 .emit_semaphore = &r600_semaphore_ring_emit,
716 }
717 },
668 .irq_set = &r600_irq_set, 718 .irq_set = &r600_irq_set,
669 .irq_process = &r600_irq_process, 719 .irq_process = &r600_irq_process,
670 .get_vblank_counter = &rs600_get_vblank_counter, 720 .get_vblank_counter = &rs600_get_vblank_counter,
671 .fence_ring_emit = &r600_fence_ring_emit,
672 .semaphore_ring_emit = &r600_semaphore_ring_emit,
673 .cs_parse = &r600_cs_parse, 721 .cs_parse = &r600_cs_parse,
674 .copy_blit = &r600_copy_blit, 722 .copy_blit = &r600_copy_blit,
675 .copy_dma = NULL, 723 .copy_dma = NULL,
@@ -711,12 +759,16 @@ static struct radeon_asic rv770_asic = {
711 .gart_tlb_flush = &r600_pcie_gart_tlb_flush, 759 .gart_tlb_flush = &r600_pcie_gart_tlb_flush,
712 .gart_set_page = &rs600_gart_set_page, 760 .gart_set_page = &rs600_gart_set_page,
713 .ring_test = &r600_ring_test, 761 .ring_test = &r600_ring_test,
714 .ring_ib_execute = &r600_ring_ib_execute, 762 .ring = {
763 [RADEON_RING_TYPE_GFX_INDEX] = {
764 .ib_execute = &r600_ring_ib_execute,
765 .emit_fence = &r600_fence_ring_emit,
766 .emit_semaphore = &r600_semaphore_ring_emit,
767 }
768 },
715 .irq_set = &r600_irq_set, 769 .irq_set = &r600_irq_set,
716 .irq_process = &r600_irq_process, 770 .irq_process = &r600_irq_process,
717 .get_vblank_counter = &rs600_get_vblank_counter, 771 .get_vblank_counter = &rs600_get_vblank_counter,
718 .fence_ring_emit = &r600_fence_ring_emit,
719 .semaphore_ring_emit = &r600_semaphore_ring_emit,
720 .cs_parse = &r600_cs_parse, 772 .cs_parse = &r600_cs_parse,
721 .copy_blit = &r600_copy_blit, 773 .copy_blit = &r600_copy_blit,
722 .copy_dma = NULL, 774 .copy_dma = NULL,
@@ -758,12 +810,16 @@ static struct radeon_asic evergreen_asic = {
758 .gart_tlb_flush = &evergreen_pcie_gart_tlb_flush, 810 .gart_tlb_flush = &evergreen_pcie_gart_tlb_flush,
759 .gart_set_page = &rs600_gart_set_page, 811 .gart_set_page = &rs600_gart_set_page,
760 .ring_test = &r600_ring_test, 812 .ring_test = &r600_ring_test,
761 .ring_ib_execute = &evergreen_ring_ib_execute, 813 .ring = {
814 [RADEON_RING_TYPE_GFX_INDEX] = {
815 .ib_execute = &evergreen_ring_ib_execute,
816 .emit_fence = &r600_fence_ring_emit,
817 .emit_semaphore = &r600_semaphore_ring_emit,
818 }
819 },
762 .irq_set = &evergreen_irq_set, 820 .irq_set = &evergreen_irq_set,
763 .irq_process = &evergreen_irq_process, 821 .irq_process = &evergreen_irq_process,
764 .get_vblank_counter = &evergreen_get_vblank_counter, 822 .get_vblank_counter = &evergreen_get_vblank_counter,
765 .fence_ring_emit = &r600_fence_ring_emit,
766 .semaphore_ring_emit = &r600_semaphore_ring_emit,
767 .cs_parse = &evergreen_cs_parse, 823 .cs_parse = &evergreen_cs_parse,
768 .copy_blit = &r600_copy_blit, 824 .copy_blit = &r600_copy_blit,
769 .copy_dma = NULL, 825 .copy_dma = NULL,
@@ -805,12 +861,16 @@ static struct radeon_asic sumo_asic = {
805 .gart_tlb_flush = &evergreen_pcie_gart_tlb_flush, 861 .gart_tlb_flush = &evergreen_pcie_gart_tlb_flush,
806 .gart_set_page = &rs600_gart_set_page, 862 .gart_set_page = &rs600_gart_set_page,
807 .ring_test = &r600_ring_test, 863 .ring_test = &r600_ring_test,
808 .ring_ib_execute = &evergreen_ring_ib_execute, 864 .ring = {
865 [RADEON_RING_TYPE_GFX_INDEX] = {
866 .ib_execute = &evergreen_ring_ib_execute,
867 .emit_fence = &r600_fence_ring_emit,
868 .emit_semaphore = &r600_semaphore_ring_emit,
869 }
870 },
809 .irq_set = &evergreen_irq_set, 871 .irq_set = &evergreen_irq_set,
810 .irq_process = &evergreen_irq_process, 872 .irq_process = &evergreen_irq_process,
811 .get_vblank_counter = &evergreen_get_vblank_counter, 873 .get_vblank_counter = &evergreen_get_vblank_counter,
812 .fence_ring_emit = &r600_fence_ring_emit,
813 .semaphore_ring_emit = &r600_semaphore_ring_emit,
814 .cs_parse = &evergreen_cs_parse, 874 .cs_parse = &evergreen_cs_parse,
815 .copy_blit = &r600_copy_blit, 875 .copy_blit = &r600_copy_blit,
816 .copy_dma = NULL, 876 .copy_dma = NULL,
@@ -852,12 +912,16 @@ static struct radeon_asic btc_asic = {
852 .gart_tlb_flush = &evergreen_pcie_gart_tlb_flush, 912 .gart_tlb_flush = &evergreen_pcie_gart_tlb_flush,
853 .gart_set_page = &rs600_gart_set_page, 913 .gart_set_page = &rs600_gart_set_page,
854 .ring_test = &r600_ring_test, 914 .ring_test = &r600_ring_test,
855 .ring_ib_execute = &evergreen_ring_ib_execute, 915 .ring = {
916 [RADEON_RING_TYPE_GFX_INDEX] = {
917 .ib_execute = &evergreen_ring_ib_execute,
918 .emit_fence = &r600_fence_ring_emit,
919 .emit_semaphore = &r600_semaphore_ring_emit,
920 }
921 },
856 .irq_set = &evergreen_irq_set, 922 .irq_set = &evergreen_irq_set,
857 .irq_process = &evergreen_irq_process, 923 .irq_process = &evergreen_irq_process,
858 .get_vblank_counter = &evergreen_get_vblank_counter, 924 .get_vblank_counter = &evergreen_get_vblank_counter,
859 .fence_ring_emit = &r600_fence_ring_emit,
860 .semaphore_ring_emit = &r600_semaphore_ring_emit,
861 .cs_parse = &evergreen_cs_parse, 925 .cs_parse = &evergreen_cs_parse,
862 .copy_blit = &r600_copy_blit, 926 .copy_blit = &r600_copy_blit,
863 .copy_dma = NULL, 927 .copy_dma = NULL,
@@ -899,12 +963,26 @@ static struct radeon_asic cayman_asic = {
899 .gart_tlb_flush = &cayman_pcie_gart_tlb_flush, 963 .gart_tlb_flush = &cayman_pcie_gart_tlb_flush,
900 .gart_set_page = &rs600_gart_set_page, 964 .gart_set_page = &rs600_gart_set_page,
901 .ring_test = &r600_ring_test, 965 .ring_test = &r600_ring_test,
902 .ring_ib_execute = &evergreen_ring_ib_execute, 966 .ring = {
967 [RADEON_RING_TYPE_GFX_INDEX] = {
968 .ib_execute = &evergreen_ring_ib_execute,
969 .emit_fence = &r600_fence_ring_emit,
970 .emit_semaphore = &r600_semaphore_ring_emit,
971 },
972 [CAYMAN_RING_TYPE_CP1_INDEX] = {
973 .ib_execute = &r600_ring_ib_execute,
974 .emit_fence = &r600_fence_ring_emit,
975 .emit_semaphore = &r600_semaphore_ring_emit,
976 },
977 [CAYMAN_RING_TYPE_CP2_INDEX] = {
978 .ib_execute = &r600_ring_ib_execute,
979 .emit_fence = &r600_fence_ring_emit,
980 .emit_semaphore = &r600_semaphore_ring_emit,
981 }
982 },
903 .irq_set = &evergreen_irq_set, 983 .irq_set = &evergreen_irq_set,
904 .irq_process = &evergreen_irq_process, 984 .irq_process = &evergreen_irq_process,
905 .get_vblank_counter = &evergreen_get_vblank_counter, 985 .get_vblank_counter = &evergreen_get_vblank_counter,
906 .fence_ring_emit = &r600_fence_ring_emit,
907 .semaphore_ring_emit = &r600_semaphore_ring_emit,
908 .cs_parse = &evergreen_cs_parse, 986 .cs_parse = &evergreen_cs_parse,
909 .copy_blit = &r600_copy_blit, 987 .copy_blit = &r600_copy_blit,
910 .copy_dma = NULL, 988 .copy_dma = NULL,