drm/radeon: implement clock and power gating for CIK (v3)

Only the APUs support power gating.

v2: disable cgcg for now
v3: workaround hw issue in mgcg

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

1 files changed, 2 insertions, 0 deletions

diff --git a/drivers/gpu/drm/radeon/radeon_asic.c b/drivers/gpu/drm/radeon/radeon_asic.c
index 1926ec06a638..880551b6df61 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.c
+++ b/drivers/gpu/drm/radeon/radeon_asic.c
@@ -2780,6 +2780,7 @@ int radeon_asic_init(struct radeon_device *rdev)
         case CHIP_BONAIRE:
                 rdev->asic = &ci_asic;
                 rdev->num_crtc = 6;
+                rdev->has_uvd = true;
                 break;
         case CHIP_KAVERI:
         case CHIP_KABINI:
@@ -2789,6 +2790,7 @@ int radeon_asic_init(struct radeon_device *rdev)
                         rdev->num_crtc = 4;
                 else
                         rdev->num_crtc = 2;
+                rdev->has_uvd = true;
                 break;
         default:
                 /* FIXME: not supported yet */