diff options
author | Alex Deucher <alexander.deucher@amd.com> | 2013-01-24 11:37:19 -0500 |
---|---|---|
committer | Alex Deucher <alexander.deucher@amd.com> | 2013-01-31 16:24:57 -0500 |
commit | 123bc1832c33218dfa677a88c2c54bc1a48a9e72 (patch) | |
tree | 5ad2423f6e4752d7db0120b8ecb4af6a83a00df2 /drivers/gpu/drm/radeon/radeon_asic.c | |
parent | f770d78ac159a96071e3c4e4ab97c262e79506d3 (diff) |
drm/radeon: use the reset mask to determine if rings are hung
fetch the reset mask and check if the relevant ring flags
are set to determine whether the ring is hung or not.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/radeon_asic.c')
-rw-r--r-- | drivers/gpu/drm/radeon/radeon_asic.c | 40 |
1 files changed, 20 insertions, 20 deletions
diff --git a/drivers/gpu/drm/radeon/radeon_asic.c b/drivers/gpu/drm/radeon/radeon_asic.c index 0b202c07fe50..82b5ef043b0e 100644 --- a/drivers/gpu/drm/radeon/radeon_asic.c +++ b/drivers/gpu/drm/radeon/radeon_asic.c | |||
@@ -946,7 +946,7 @@ static struct radeon_asic r600_asic = { | |||
946 | .cs_parse = &r600_cs_parse, | 946 | .cs_parse = &r600_cs_parse, |
947 | .ring_test = &r600_ring_test, | 947 | .ring_test = &r600_ring_test, |
948 | .ib_test = &r600_ib_test, | 948 | .ib_test = &r600_ib_test, |
949 | .is_lockup = &r600_gpu_is_lockup, | 949 | .is_lockup = &r600_gfx_is_lockup, |
950 | }, | 950 | }, |
951 | [R600_RING_TYPE_DMA_INDEX] = { | 951 | [R600_RING_TYPE_DMA_INDEX] = { |
952 | .ib_execute = &r600_dma_ring_ib_execute, | 952 | .ib_execute = &r600_dma_ring_ib_execute, |
@@ -1030,7 +1030,7 @@ static struct radeon_asic rs780_asic = { | |||
1030 | .cs_parse = &r600_cs_parse, | 1030 | .cs_parse = &r600_cs_parse, |
1031 | .ring_test = &r600_ring_test, | 1031 | .ring_test = &r600_ring_test, |
1032 | .ib_test = &r600_ib_test, | 1032 | .ib_test = &r600_ib_test, |
1033 | .is_lockup = &r600_gpu_is_lockup, | 1033 | .is_lockup = &r600_gfx_is_lockup, |
1034 | }, | 1034 | }, |
1035 | [R600_RING_TYPE_DMA_INDEX] = { | 1035 | [R600_RING_TYPE_DMA_INDEX] = { |
1036 | .ib_execute = &r600_dma_ring_ib_execute, | 1036 | .ib_execute = &r600_dma_ring_ib_execute, |
@@ -1114,7 +1114,7 @@ static struct radeon_asic rv770_asic = { | |||
1114 | .cs_parse = &r600_cs_parse, | 1114 | .cs_parse = &r600_cs_parse, |
1115 | .ring_test = &r600_ring_test, | 1115 | .ring_test = &r600_ring_test, |
1116 | .ib_test = &r600_ib_test, | 1116 | .ib_test = &r600_ib_test, |
1117 | .is_lockup = &r600_gpu_is_lockup, | 1117 | .is_lockup = &r600_gfx_is_lockup, |
1118 | }, | 1118 | }, |
1119 | [R600_RING_TYPE_DMA_INDEX] = { | 1119 | [R600_RING_TYPE_DMA_INDEX] = { |
1120 | .ib_execute = &r600_dma_ring_ib_execute, | 1120 | .ib_execute = &r600_dma_ring_ib_execute, |
@@ -1198,7 +1198,7 @@ static struct radeon_asic evergreen_asic = { | |||
1198 | .cs_parse = &evergreen_cs_parse, | 1198 | .cs_parse = &evergreen_cs_parse, |
1199 | .ring_test = &r600_ring_test, | 1199 | .ring_test = &r600_ring_test, |
1200 | .ib_test = &r600_ib_test, | 1200 | .ib_test = &r600_ib_test, |
1201 | .is_lockup = &evergreen_gpu_is_lockup, | 1201 | .is_lockup = &evergreen_gfx_is_lockup, |
1202 | }, | 1202 | }, |
1203 | [R600_RING_TYPE_DMA_INDEX] = { | 1203 | [R600_RING_TYPE_DMA_INDEX] = { |
1204 | .ib_execute = &evergreen_dma_ring_ib_execute, | 1204 | .ib_execute = &evergreen_dma_ring_ib_execute, |
@@ -1207,7 +1207,7 @@ static struct radeon_asic evergreen_asic = { | |||
1207 | .cs_parse = &evergreen_dma_cs_parse, | 1207 | .cs_parse = &evergreen_dma_cs_parse, |
1208 | .ring_test = &r600_dma_ring_test, | 1208 | .ring_test = &r600_dma_ring_test, |
1209 | .ib_test = &r600_dma_ib_test, | 1209 | .ib_test = &r600_dma_ib_test, |
1210 | .is_lockup = &r600_dma_is_lockup, | 1210 | .is_lockup = &evergreen_dma_is_lockup, |
1211 | } | 1211 | } |
1212 | }, | 1212 | }, |
1213 | .irq = { | 1213 | .irq = { |
@@ -1282,7 +1282,7 @@ static struct radeon_asic sumo_asic = { | |||
1282 | .cs_parse = &evergreen_cs_parse, | 1282 | .cs_parse = &evergreen_cs_parse, |
1283 | .ring_test = &r600_ring_test, | 1283 | .ring_test = &r600_ring_test, |
1284 | .ib_test = &r600_ib_test, | 1284 | .ib_test = &r600_ib_test, |
1285 | .is_lockup = &evergreen_gpu_is_lockup, | 1285 | .is_lockup = &evergreen_gfx_is_lockup, |
1286 | }, | 1286 | }, |
1287 | [R600_RING_TYPE_DMA_INDEX] = { | 1287 | [R600_RING_TYPE_DMA_INDEX] = { |
1288 | .ib_execute = &evergreen_dma_ring_ib_execute, | 1288 | .ib_execute = &evergreen_dma_ring_ib_execute, |
@@ -1291,7 +1291,7 @@ static struct radeon_asic sumo_asic = { | |||
1291 | .cs_parse = &evergreen_dma_cs_parse, | 1291 | .cs_parse = &evergreen_dma_cs_parse, |
1292 | .ring_test = &r600_dma_ring_test, | 1292 | .ring_test = &r600_dma_ring_test, |
1293 | .ib_test = &r600_dma_ib_test, | 1293 | .ib_test = &r600_dma_ib_test, |
1294 | .is_lockup = &r600_dma_is_lockup, | 1294 | .is_lockup = &evergreen_dma_is_lockup, |
1295 | } | 1295 | } |
1296 | }, | 1296 | }, |
1297 | .irq = { | 1297 | .irq = { |
@@ -1366,7 +1366,7 @@ static struct radeon_asic btc_asic = { | |||
1366 | .cs_parse = &evergreen_cs_parse, | 1366 | .cs_parse = &evergreen_cs_parse, |
1367 | .ring_test = &r600_ring_test, | 1367 | .ring_test = &r600_ring_test, |
1368 | .ib_test = &r600_ib_test, | 1368 | .ib_test = &r600_ib_test, |
1369 | .is_lockup = &evergreen_gpu_is_lockup, | 1369 | .is_lockup = &evergreen_gfx_is_lockup, |
1370 | }, | 1370 | }, |
1371 | [R600_RING_TYPE_DMA_INDEX] = { | 1371 | [R600_RING_TYPE_DMA_INDEX] = { |
1372 | .ib_execute = &evergreen_dma_ring_ib_execute, | 1372 | .ib_execute = &evergreen_dma_ring_ib_execute, |
@@ -1375,7 +1375,7 @@ static struct radeon_asic btc_asic = { | |||
1375 | .cs_parse = &evergreen_dma_cs_parse, | 1375 | .cs_parse = &evergreen_dma_cs_parse, |
1376 | .ring_test = &r600_dma_ring_test, | 1376 | .ring_test = &r600_dma_ring_test, |
1377 | .ib_test = &r600_dma_ib_test, | 1377 | .ib_test = &r600_dma_ib_test, |
1378 | .is_lockup = &r600_dma_is_lockup, | 1378 | .is_lockup = &evergreen_dma_is_lockup, |
1379 | } | 1379 | } |
1380 | }, | 1380 | }, |
1381 | .irq = { | 1381 | .irq = { |
@@ -1457,7 +1457,7 @@ static struct radeon_asic cayman_asic = { | |||
1457 | .cs_parse = &evergreen_cs_parse, | 1457 | .cs_parse = &evergreen_cs_parse, |
1458 | .ring_test = &r600_ring_test, | 1458 | .ring_test = &r600_ring_test, |
1459 | .ib_test = &r600_ib_test, | 1459 | .ib_test = &r600_ib_test, |
1460 | .is_lockup = &evergreen_gpu_is_lockup, | 1460 | .is_lockup = &cayman_gfx_is_lockup, |
1461 | .vm_flush = &cayman_vm_flush, | 1461 | .vm_flush = &cayman_vm_flush, |
1462 | }, | 1462 | }, |
1463 | [CAYMAN_RING_TYPE_CP1_INDEX] = { | 1463 | [CAYMAN_RING_TYPE_CP1_INDEX] = { |
@@ -1468,7 +1468,7 @@ static struct radeon_asic cayman_asic = { | |||
1468 | .cs_parse = &evergreen_cs_parse, | 1468 | .cs_parse = &evergreen_cs_parse, |
1469 | .ring_test = &r600_ring_test, | 1469 | .ring_test = &r600_ring_test, |
1470 | .ib_test = &r600_ib_test, | 1470 | .ib_test = &r600_ib_test, |
1471 | .is_lockup = &evergreen_gpu_is_lockup, | 1471 | .is_lockup = &cayman_gfx_is_lockup, |
1472 | .vm_flush = &cayman_vm_flush, | 1472 | .vm_flush = &cayman_vm_flush, |
1473 | }, | 1473 | }, |
1474 | [CAYMAN_RING_TYPE_CP2_INDEX] = { | 1474 | [CAYMAN_RING_TYPE_CP2_INDEX] = { |
@@ -1479,7 +1479,7 @@ static struct radeon_asic cayman_asic = { | |||
1479 | .cs_parse = &evergreen_cs_parse, | 1479 | .cs_parse = &evergreen_cs_parse, |
1480 | .ring_test = &r600_ring_test, | 1480 | .ring_test = &r600_ring_test, |
1481 | .ib_test = &r600_ib_test, | 1481 | .ib_test = &r600_ib_test, |
1482 | .is_lockup = &evergreen_gpu_is_lockup, | 1482 | .is_lockup = &cayman_gfx_is_lockup, |
1483 | .vm_flush = &cayman_vm_flush, | 1483 | .vm_flush = &cayman_vm_flush, |
1484 | }, | 1484 | }, |
1485 | [R600_RING_TYPE_DMA_INDEX] = { | 1485 | [R600_RING_TYPE_DMA_INDEX] = { |
@@ -1584,7 +1584,7 @@ static struct radeon_asic trinity_asic = { | |||
1584 | .cs_parse = &evergreen_cs_parse, | 1584 | .cs_parse = &evergreen_cs_parse, |
1585 | .ring_test = &r600_ring_test, | 1585 | .ring_test = &r600_ring_test, |
1586 | .ib_test = &r600_ib_test, | 1586 | .ib_test = &r600_ib_test, |
1587 | .is_lockup = &evergreen_gpu_is_lockup, | 1587 | .is_lockup = &cayman_gfx_is_lockup, |
1588 | .vm_flush = &cayman_vm_flush, | 1588 | .vm_flush = &cayman_vm_flush, |
1589 | }, | 1589 | }, |
1590 | [CAYMAN_RING_TYPE_CP1_INDEX] = { | 1590 | [CAYMAN_RING_TYPE_CP1_INDEX] = { |
@@ -1595,7 +1595,7 @@ static struct radeon_asic trinity_asic = { | |||
1595 | .cs_parse = &evergreen_cs_parse, | 1595 | .cs_parse = &evergreen_cs_parse, |
1596 | .ring_test = &r600_ring_test, | 1596 | .ring_test = &r600_ring_test, |
1597 | .ib_test = &r600_ib_test, | 1597 | .ib_test = &r600_ib_test, |
1598 | .is_lockup = &evergreen_gpu_is_lockup, | 1598 | .is_lockup = &cayman_gfx_is_lockup, |
1599 | .vm_flush = &cayman_vm_flush, | 1599 | .vm_flush = &cayman_vm_flush, |
1600 | }, | 1600 | }, |
1601 | [CAYMAN_RING_TYPE_CP2_INDEX] = { | 1601 | [CAYMAN_RING_TYPE_CP2_INDEX] = { |
@@ -1606,7 +1606,7 @@ static struct radeon_asic trinity_asic = { | |||
1606 | .cs_parse = &evergreen_cs_parse, | 1606 | .cs_parse = &evergreen_cs_parse, |
1607 | .ring_test = &r600_ring_test, | 1607 | .ring_test = &r600_ring_test, |
1608 | .ib_test = &r600_ib_test, | 1608 | .ib_test = &r600_ib_test, |
1609 | .is_lockup = &evergreen_gpu_is_lockup, | 1609 | .is_lockup = &cayman_gfx_is_lockup, |
1610 | .vm_flush = &cayman_vm_flush, | 1610 | .vm_flush = &cayman_vm_flush, |
1611 | }, | 1611 | }, |
1612 | [R600_RING_TYPE_DMA_INDEX] = { | 1612 | [R600_RING_TYPE_DMA_INDEX] = { |
@@ -1711,7 +1711,7 @@ static struct radeon_asic si_asic = { | |||
1711 | .cs_parse = NULL, | 1711 | .cs_parse = NULL, |
1712 | .ring_test = &r600_ring_test, | 1712 | .ring_test = &r600_ring_test, |
1713 | .ib_test = &r600_ib_test, | 1713 | .ib_test = &r600_ib_test, |
1714 | .is_lockup = &si_gpu_is_lockup, | 1714 | .is_lockup = &si_gfx_is_lockup, |
1715 | .vm_flush = &si_vm_flush, | 1715 | .vm_flush = &si_vm_flush, |
1716 | }, | 1716 | }, |
1717 | [CAYMAN_RING_TYPE_CP1_INDEX] = { | 1717 | [CAYMAN_RING_TYPE_CP1_INDEX] = { |
@@ -1722,7 +1722,7 @@ static struct radeon_asic si_asic = { | |||
1722 | .cs_parse = NULL, | 1722 | .cs_parse = NULL, |
1723 | .ring_test = &r600_ring_test, | 1723 | .ring_test = &r600_ring_test, |
1724 | .ib_test = &r600_ib_test, | 1724 | .ib_test = &r600_ib_test, |
1725 | .is_lockup = &si_gpu_is_lockup, | 1725 | .is_lockup = &si_gfx_is_lockup, |
1726 | .vm_flush = &si_vm_flush, | 1726 | .vm_flush = &si_vm_flush, |
1727 | }, | 1727 | }, |
1728 | [CAYMAN_RING_TYPE_CP2_INDEX] = { | 1728 | [CAYMAN_RING_TYPE_CP2_INDEX] = { |
@@ -1733,7 +1733,7 @@ static struct radeon_asic si_asic = { | |||
1733 | .cs_parse = NULL, | 1733 | .cs_parse = NULL, |
1734 | .ring_test = &r600_ring_test, | 1734 | .ring_test = &r600_ring_test, |
1735 | .ib_test = &r600_ib_test, | 1735 | .ib_test = &r600_ib_test, |
1736 | .is_lockup = &si_gpu_is_lockup, | 1736 | .is_lockup = &si_gfx_is_lockup, |
1737 | .vm_flush = &si_vm_flush, | 1737 | .vm_flush = &si_vm_flush, |
1738 | }, | 1738 | }, |
1739 | [R600_RING_TYPE_DMA_INDEX] = { | 1739 | [R600_RING_TYPE_DMA_INDEX] = { |
@@ -1744,7 +1744,7 @@ static struct radeon_asic si_asic = { | |||
1744 | .cs_parse = NULL, | 1744 | .cs_parse = NULL, |
1745 | .ring_test = &r600_dma_ring_test, | 1745 | .ring_test = &r600_dma_ring_test, |
1746 | .ib_test = &r600_dma_ib_test, | 1746 | .ib_test = &r600_dma_ib_test, |
1747 | .is_lockup = &cayman_dma_is_lockup, | 1747 | .is_lockup = &si_dma_is_lockup, |
1748 | .vm_flush = &si_dma_vm_flush, | 1748 | .vm_flush = &si_dma_vm_flush, |
1749 | }, | 1749 | }, |
1750 | [CAYMAN_RING_TYPE_DMA1_INDEX] = { | 1750 | [CAYMAN_RING_TYPE_DMA1_INDEX] = { |
@@ -1755,7 +1755,7 @@ static struct radeon_asic si_asic = { | |||
1755 | .cs_parse = NULL, | 1755 | .cs_parse = NULL, |
1756 | .ring_test = &r600_dma_ring_test, | 1756 | .ring_test = &r600_dma_ring_test, |
1757 | .ib_test = &r600_dma_ib_test, | 1757 | .ib_test = &r600_dma_ib_test, |
1758 | .is_lockup = &cayman_dma_is_lockup, | 1758 | .is_lockup = &si_dma_is_lockup, |
1759 | .vm_flush = &si_dma_vm_flush, | 1759 | .vm_flush = &si_dma_vm_flush, |
1760 | } | 1760 | } |
1761 | }, | 1761 | }, |