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authorAlex Deucher <alexander.deucher@amd.com>2012-02-23 17:53:49 -0500
committerDave Airlie <airlied@redhat.com>2012-02-29 05:15:25 -0500
commit9e6f3d02c4d28e68a73d100f7719440196f636de (patch)
tree0885c4be2b740cd2f19c9d100fbce6ed7e737b6e /drivers/gpu/drm/radeon/radeon_asic.c
parent798bcf7341cd434f89a4ddd6882ac043b1399825 (diff)
drm/radeon/kms: reorganize surface callbacks
tidy up the radeon_asic struct. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König<christian.koenig@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/radeon_asic.c')
-rw-r--r--drivers/gpu/drm/radeon/radeon_asic.c103
1 files changed, 68 insertions, 35 deletions
diff --git a/drivers/gpu/drm/radeon/radeon_asic.c b/drivers/gpu/drm/radeon/radeon_asic.c
index 4eaa5f1209b2..0a59f4810187 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.c
+++ b/drivers/gpu/drm/radeon/radeon_asic.c
@@ -168,8 +168,10 @@ static struct radeon_asic r100_asic = {
168 .copy = &r100_copy_blit, 168 .copy = &r100_copy_blit,
169 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 169 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
170 }, 170 },
171 .set_surface_reg = r100_set_surface_reg, 171 .surface = {
172 .clear_surface_reg = r100_clear_surface_reg, 172 .set_reg = r100_set_surface_reg,
173 .clear_reg = r100_clear_surface_reg,
174 },
173 .hpd = { 175 .hpd = {
174 .init = &r100_hpd_init, 176 .init = &r100_hpd_init,
175 .fini = &r100_hpd_fini, 177 .fini = &r100_hpd_fini,
@@ -240,8 +242,10 @@ static struct radeon_asic r200_asic = {
240 .copy = &r100_copy_blit, 242 .copy = &r100_copy_blit,
241 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 243 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
242 }, 244 },
243 .set_surface_reg = r100_set_surface_reg, 245 .surface = {
244 .clear_surface_reg = r100_clear_surface_reg, 246 .set_reg = r100_set_surface_reg,
247 .clear_reg = r100_clear_surface_reg,
248 },
245 .hpd = { 249 .hpd = {
246 .init = &r100_hpd_init, 250 .init = &r100_hpd_init,
247 .fini = &r100_hpd_fini, 251 .fini = &r100_hpd_fini,
@@ -312,8 +316,10 @@ static struct radeon_asic r300_asic = {
312 .copy = &r100_copy_blit, 316 .copy = &r100_copy_blit,
313 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 317 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
314 }, 318 },
315 .set_surface_reg = r100_set_surface_reg, 319 .surface = {
316 .clear_surface_reg = r100_clear_surface_reg, 320 .set_reg = r100_set_surface_reg,
321 .clear_reg = r100_clear_surface_reg,
322 },
317 .hpd = { 323 .hpd = {
318 .init = &r100_hpd_init, 324 .init = &r100_hpd_init,
319 .fini = &r100_hpd_fini, 325 .fini = &r100_hpd_fini,
@@ -384,8 +390,10 @@ static struct radeon_asic r300_asic_pcie = {
384 .copy = &r100_copy_blit, 390 .copy = &r100_copy_blit,
385 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 391 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
386 }, 392 },
387 .set_surface_reg = r100_set_surface_reg, 393 .surface = {
388 .clear_surface_reg = r100_clear_surface_reg, 394 .set_reg = r100_set_surface_reg,
395 .clear_reg = r100_clear_surface_reg,
396 },
389 .hpd = { 397 .hpd = {
390 .init = &r100_hpd_init, 398 .init = &r100_hpd_init,
391 .fini = &r100_hpd_fini, 399 .fini = &r100_hpd_fini,
@@ -456,9 +464,10 @@ static struct radeon_asic r420_asic = {
456 .copy = &r100_copy_blit, 464 .copy = &r100_copy_blit,
457 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 465 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
458 }, 466 },
459 .set_surface_reg = r100_set_surface_reg, 467 .surface = {
460 .clear_surface_reg = r100_clear_surface_reg, 468 .set_reg = r100_set_surface_reg,
461 469 .clear_reg = r100_clear_surface_reg,
470 },
462 .hpd = { 471 .hpd = {
463 .init = &r100_hpd_init, 472 .init = &r100_hpd_init,
464 .fini = &r100_hpd_fini, 473 .fini = &r100_hpd_fini,
@@ -529,8 +538,10 @@ static struct radeon_asic rs400_asic = {
529 .copy = &r100_copy_blit, 538 .copy = &r100_copy_blit,
530 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 539 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
531 }, 540 },
532 .set_surface_reg = r100_set_surface_reg, 541 .surface = {
533 .clear_surface_reg = r100_clear_surface_reg, 542 .set_reg = r100_set_surface_reg,
543 .clear_reg = r100_clear_surface_reg,
544 },
534 .hpd = { 545 .hpd = {
535 .init = &r100_hpd_init, 546 .init = &r100_hpd_init,
536 .fini = &r100_hpd_fini, 547 .fini = &r100_hpd_fini,
@@ -601,8 +612,10 @@ static struct radeon_asic rs600_asic = {
601 .copy = &r100_copy_blit, 612 .copy = &r100_copy_blit,
602 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 613 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
603 }, 614 },
604 .set_surface_reg = r100_set_surface_reg, 615 .surface = {
605 .clear_surface_reg = r100_clear_surface_reg, 616 .set_reg = r100_set_surface_reg,
617 .clear_reg = r100_clear_surface_reg,
618 },
606 .hpd = { 619 .hpd = {
607 .init = &rs600_hpd_init, 620 .init = &rs600_hpd_init,
608 .fini = &rs600_hpd_fini, 621 .fini = &rs600_hpd_fini,
@@ -673,8 +686,10 @@ static struct radeon_asic rs690_asic = {
673 .copy = &r200_copy_dma, 686 .copy = &r200_copy_dma,
674 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 687 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
675 }, 688 },
676 .set_surface_reg = r100_set_surface_reg, 689 .surface = {
677 .clear_surface_reg = r100_clear_surface_reg, 690 .set_reg = r100_set_surface_reg,
691 .clear_reg = r100_clear_surface_reg,
692 },
678 .hpd = { 693 .hpd = {
679 .init = &rs600_hpd_init, 694 .init = &rs600_hpd_init,
680 .fini = &rs600_hpd_fini, 695 .fini = &rs600_hpd_fini,
@@ -745,8 +760,10 @@ static struct radeon_asic rv515_asic = {
745 .copy = &r100_copy_blit, 760 .copy = &r100_copy_blit,
746 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 761 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
747 }, 762 },
748 .set_surface_reg = r100_set_surface_reg, 763 .surface = {
749 .clear_surface_reg = r100_clear_surface_reg, 764 .set_reg = r100_set_surface_reg,
765 .clear_reg = r100_clear_surface_reg,
766 },
750 .hpd = { 767 .hpd = {
751 .init = &rs600_hpd_init, 768 .init = &rs600_hpd_init,
752 .fini = &rs600_hpd_fini, 769 .fini = &rs600_hpd_fini,
@@ -817,8 +834,10 @@ static struct radeon_asic r520_asic = {
817 .copy = &r100_copy_blit, 834 .copy = &r100_copy_blit,
818 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 835 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
819 }, 836 },
820 .set_surface_reg = r100_set_surface_reg, 837 .surface = {
821 .clear_surface_reg = r100_clear_surface_reg, 838 .set_reg = r100_set_surface_reg,
839 .clear_reg = r100_clear_surface_reg,
840 },
822 .hpd = { 841 .hpd = {
823 .init = &rs600_hpd_init, 842 .init = &rs600_hpd_init,
824 .fini = &rs600_hpd_fini, 843 .fini = &rs600_hpd_fini,
@@ -888,8 +907,10 @@ static struct radeon_asic r600_asic = {
888 .copy = &r600_copy_blit, 907 .copy = &r600_copy_blit,
889 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 908 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
890 }, 909 },
891 .set_surface_reg = r600_set_surface_reg, 910 .surface = {
892 .clear_surface_reg = r600_clear_surface_reg, 911 .set_reg = r600_set_surface_reg,
912 .clear_reg = r600_clear_surface_reg,
913 },
893 .hpd = { 914 .hpd = {
894 .init = &r600_hpd_init, 915 .init = &r600_hpd_init,
895 .fini = &r600_hpd_fini, 916 .fini = &r600_hpd_fini,
@@ -959,8 +980,10 @@ static struct radeon_asic rs780_asic = {
959 .copy = &r600_copy_blit, 980 .copy = &r600_copy_blit,
960 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 981 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
961 }, 982 },
962 .set_surface_reg = r600_set_surface_reg, 983 .surface = {
963 .clear_surface_reg = r600_clear_surface_reg, 984 .set_reg = r600_set_surface_reg,
985 .clear_reg = r600_clear_surface_reg,
986 },
964 .hpd = { 987 .hpd = {
965 .init = &r600_hpd_init, 988 .init = &r600_hpd_init,
966 .fini = &r600_hpd_fini, 989 .fini = &r600_hpd_fini,
@@ -1030,8 +1053,10 @@ static struct radeon_asic rv770_asic = {
1030 .copy = &r600_copy_blit, 1053 .copy = &r600_copy_blit,
1031 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1054 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1032 }, 1055 },
1033 .set_surface_reg = r600_set_surface_reg, 1056 .surface = {
1034 .clear_surface_reg = r600_clear_surface_reg, 1057 .set_reg = r600_set_surface_reg,
1058 .clear_reg = r600_clear_surface_reg,
1059 },
1035 .hpd = { 1060 .hpd = {
1036 .init = &r600_hpd_init, 1061 .init = &r600_hpd_init,
1037 .fini = &r600_hpd_fini, 1062 .fini = &r600_hpd_fini,
@@ -1101,8 +1126,10 @@ static struct radeon_asic evergreen_asic = {
1101 .copy = &r600_copy_blit, 1126 .copy = &r600_copy_blit,
1102 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1127 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1103 }, 1128 },
1104 .set_surface_reg = r600_set_surface_reg, 1129 .surface = {
1105 .clear_surface_reg = r600_clear_surface_reg, 1130 .set_reg = r600_set_surface_reg,
1131 .clear_reg = r600_clear_surface_reg,
1132 },
1106 .hpd = { 1133 .hpd = {
1107 .init = &evergreen_hpd_init, 1134 .init = &evergreen_hpd_init,
1108 .fini = &evergreen_hpd_fini, 1135 .fini = &evergreen_hpd_fini,
@@ -1172,8 +1199,10 @@ static struct radeon_asic sumo_asic = {
1172 .copy = &r600_copy_blit, 1199 .copy = &r600_copy_blit,
1173 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1200 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1174 }, 1201 },
1175 .set_surface_reg = r600_set_surface_reg, 1202 .surface = {
1176 .clear_surface_reg = r600_clear_surface_reg, 1203 .set_reg = r600_set_surface_reg,
1204 .clear_reg = r600_clear_surface_reg,
1205 },
1177 .hpd = { 1206 .hpd = {
1178 .init = &evergreen_hpd_init, 1207 .init = &evergreen_hpd_init,
1179 .fini = &evergreen_hpd_fini, 1208 .fini = &evergreen_hpd_fini,
@@ -1243,8 +1272,10 @@ static struct radeon_asic btc_asic = {
1243 .copy = &r600_copy_blit, 1272 .copy = &r600_copy_blit,
1244 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1273 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1245 }, 1274 },
1246 .set_surface_reg = r600_set_surface_reg, 1275 .surface = {
1247 .clear_surface_reg = r600_clear_surface_reg, 1276 .set_reg = r600_set_surface_reg,
1277 .clear_reg = r600_clear_surface_reg,
1278 },
1248 .hpd = { 1279 .hpd = {
1249 .init = &evergreen_hpd_init, 1280 .init = &evergreen_hpd_init,
1250 .fini = &evergreen_hpd_fini, 1281 .fini = &evergreen_hpd_fini,
@@ -1343,8 +1374,10 @@ static struct radeon_asic cayman_asic = {
1343 .copy = &r600_copy_blit, 1374 .copy = &r600_copy_blit,
1344 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1375 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1345 }, 1376 },
1346 .set_surface_reg = r600_set_surface_reg, 1377 .surface = {
1347 .clear_surface_reg = r600_clear_surface_reg, 1378 .set_reg = r600_set_surface_reg,
1379 .clear_reg = r600_clear_surface_reg,
1380 },
1348 .hpd = { 1381 .hpd = {
1349 .init = &evergreen_hpd_init, 1382 .init = &evergreen_hpd_init,
1350 .fini = &evergreen_hpd_fini, 1383 .fini = &evergreen_hpd_fini,
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-05 11:15:20 -0500