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authorJerome Glisse <jglisse@redhat.com>2010-03-09 09:45:12 -0500
committerDave Airlie <airlied@redhat.com>2010-04-05 21:21:11 -0400
commit90aca4d2740255bd130ea71a91530b9920c70abe (patch)
treeacf9b8a4353e6727cd6cba5b71caaf9f067e465d /drivers/gpu/drm/radeon/radeon_asic.c
parenta2d07b7438f015a0349bc9af3c96a8164549bbc5 (diff)
drm/radeon/kms: simplify & improve GPU reset V2
This simplify and improve GPU reset for R1XX-R6XX hw, it's not 100% reliable here are result: - R1XX/R2XX works bunch of time in a row, sometimes it seems it can work indifinitly - R3XX/R3XX the most unreliable one, sometimes you will be able to reset few times, sometimes not even once - R5XX more reliable than previous hw, seems to work most of the times but once in a while it fails for no obvious reasons (same status than previous reset just no same happy ending) - R6XX/R7XX are lot more reliable with this patch, still it seems that it can fail after a bunch (reset every 2sec for 3hour bring down the GPU & computer) This have been tested on various hw, for some odd reasons i wasn't able to lockup RS480/RS690 (while they use to love locking up). Note that on R1XX-R5XX the cursor will disapear after lockup haven't checked why, switch to console and back to X will restore cursor. Next step is to record the bogus command that leaded to the lockup. V2 Fix r6xx resume path to avoid reinitializing blit module, use the gpu_lockup boolean to avoid entering inifinite waiting loop on fence while reiniting the GPU Signed-off-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/radeon_asic.c')
-rw-r--r--drivers/gpu/drm/radeon/radeon_asic.c9
1 files changed, 5 insertions, 4 deletions
diff --git a/drivers/gpu/drm/radeon/radeon_asic.c b/drivers/gpu/drm/radeon/radeon_asic.c
index 011ac6d86581..0d7664b8e489 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.c
+++ b/drivers/gpu/drm/radeon/radeon_asic.c
@@ -367,7 +367,7 @@ static struct radeon_asic rs600_asic = {
367 .resume = &rs600_resume, 367 .resume = &rs600_resume,
368 .vga_set_state = &r100_vga_set_state, 368 .vga_set_state = &r100_vga_set_state,
369 .gpu_is_lockup = &r300_gpu_is_lockup, 369 .gpu_is_lockup = &r300_gpu_is_lockup,
370 .asic_reset = &r300_asic_reset, 370 .asic_reset = &rs600_asic_reset,
371 .gart_tlb_flush = &rs600_gart_tlb_flush, 371 .gart_tlb_flush = &rs600_gart_tlb_flush,
372 .gart_set_page = &rs600_gart_set_page, 372 .gart_set_page = &rs600_gart_set_page,
373 .cp_commit = &r100_cp_commit, 373 .cp_commit = &r100_cp_commit,
@@ -406,7 +406,7 @@ static struct radeon_asic rs690_asic = {
406 .resume = &rs690_resume, 406 .resume = &rs690_resume,
407 .vga_set_state = &r100_vga_set_state, 407 .vga_set_state = &r100_vga_set_state,
408 .gpu_is_lockup = &r300_gpu_is_lockup, 408 .gpu_is_lockup = &r300_gpu_is_lockup,
409 .asic_reset = &r300_asic_reset, 409 .asic_reset = &rs600_asic_reset,
410 .gart_tlb_flush = &rs400_gart_tlb_flush, 410 .gart_tlb_flush = &rs400_gart_tlb_flush,
411 .gart_set_page = &rs400_gart_set_page, 411 .gart_set_page = &rs400_gart_set_page,
412 .cp_commit = &r100_cp_commit, 412 .cp_commit = &r100_cp_commit,
@@ -445,7 +445,7 @@ static struct radeon_asic rv515_asic = {
445 .resume = &rv515_resume, 445 .resume = &rv515_resume,
446 .vga_set_state = &r100_vga_set_state, 446 .vga_set_state = &r100_vga_set_state,
447 .gpu_is_lockup = &r300_gpu_is_lockup, 447 .gpu_is_lockup = &r300_gpu_is_lockup,
448 .asic_reset = &rv515_asic_reset, 448 .asic_reset = &rs600_asic_reset,
449 .gart_tlb_flush = &rv370_pcie_gart_tlb_flush, 449 .gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
450 .gart_set_page = &rv370_pcie_gart_set_page, 450 .gart_set_page = &rv370_pcie_gart_set_page,
451 .cp_commit = &r100_cp_commit, 451 .cp_commit = &r100_cp_commit,
@@ -484,7 +484,7 @@ static struct radeon_asic r520_asic = {
484 .resume = &r520_resume, 484 .resume = &r520_resume,
485 .vga_set_state = &r100_vga_set_state, 485 .vga_set_state = &r100_vga_set_state,
486 .gpu_is_lockup = &r300_gpu_is_lockup, 486 .gpu_is_lockup = &r300_gpu_is_lockup,
487 .asic_reset = &rv515_asic_reset, 487 .asic_reset = &rs600_asic_reset,
488 .gart_tlb_flush = &rv370_pcie_gart_tlb_flush, 488 .gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
489 .gart_set_page = &rv370_pcie_gart_set_page, 489 .gart_set_page = &rv370_pcie_gart_set_page,
490 .cp_commit = &r100_cp_commit, 490 .cp_commit = &r100_cp_commit,
@@ -560,6 +560,7 @@ static struct radeon_asic rs780_asic = {
560 .suspend = &r600_suspend, 560 .suspend = &r600_suspend,
561 .resume = &r600_resume, 561 .resume = &r600_resume,
562 .cp_commit = &r600_cp_commit, 562 .cp_commit = &r600_cp_commit,
563 .gpu_is_lockup = &r600_gpu_is_lockup,
563 .vga_set_state = &r600_vga_set_state, 564 .vga_set_state = &r600_vga_set_state,
564 .asic_reset = &r600_asic_reset, 565 .asic_reset = &r600_asic_reset,
565 .gart_tlb_flush = &r600_pcie_gart_tlb_flush, 566 .gart_tlb_flush = &r600_pcie_gart_tlb_flush,