drm/radeon: convert fence to uint64_t v4

This convert fence to use uint64_t sequence number intention is
to use the fact that uin64_t is big enough that we don't need to
care about wrap around.

Tested with and without writeback using 0xFFFFF000 as initial
fence sequence and thus allowing to test the wrap around from
32bits to 64bits.

v2: Add comment about possible race btw CPU & GPU, add comment
    stressing that we need 2 dword aligned for R600_WB_EVENT_OFFSET
    Read fence sequenc in reverse order of GPU write them so we
    mitigate the race btw CPU and GPU.

v3: Drop the need for ring to emit the 64bits fence, and just have
    each ring emit the lower 32bits of the fence sequence. We
    handle the wrap over 32bits in fence_process.

v4: Just a small optimization: Don't reread the last_seq value
    if loop restarts, since we already know its value anyway.
    Also start at zero not one for seq value and use pre instead
    of post increment in emmit, otherwise wait_empty will deadlock.

Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Christian König <deathsimple@vodafone.de>
Signed-off-by: Dave Airlie <airlied@redhat.com>

1 files changed, 21 insertions, 18 deletions

diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index e99ea816d8c9..cdf46bc6dcc4 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -100,28 +100,32 @@ extern int radeon_lockup_timeout;
  * Copy from radeon_drv.h so we don't have to include both and have conflicting
  * symbol;
  */
-#define RADEON_MAX_USEC_TIMEOUT         100000  /* 100 ms */
-#define RADEON_FENCE_JIFFIES_TIMEOUT    (HZ / 2)
+#define RADEON_MAX_USEC_TIMEOUT                 100000  /* 100 ms */
+#define RADEON_FENCE_JIFFIES_TIMEOUT            (HZ / 2)
 /* RADEON_IB_POOL_SIZE must be a power of 2 */
-#define RADEON_IB_POOL_SIZE             16
-#define RADEON_DEBUGFS_MAX_COMPONENTS   32
-#define RADEONFB_CONN_LIMIT             4
-#define RADEON_BIOS_NUM_SCRATCH         8
+#define RADEON_IB_POOL_SIZE                     16
+#define RADEON_DEBUGFS_MAX_COMPONENTS           32
+#define RADEONFB_CONN_LIMIT                     4
+#define RADEON_BIOS_NUM_SCRATCH                 8
 
 /* max number of rings */
-#define RADEON_NUM_RINGS 3
+#define RADEON_NUM_RINGS                        3
+
+/* fence seq are set to this number when signaled */
+#define RADEON_FENCE_SIGNALED_SEQ               0LL
+#define RADEON_FENCE_NOTEMITED_SEQ              (~0LL)
 
 /* internal ring indices */
 /* r1xx+ has gfx CP ring */
-#define RADEON_RING_TYPE_GFX_INDEX  0
+#define RADEON_RING_TYPE_GFX_INDEX              0
 
 /* cayman has 2 compute CP rings */
-#define CAYMAN_RING_TYPE_CP1_INDEX 1
-#define CAYMAN_RING_TYPE_CP2_INDEX 2
+#define CAYMAN_RING_TYPE_CP1_INDEX              1
+#define CAYMAN_RING_TYPE_CP2_INDEX              2
 
 /* hardcode those limit for now */
-#define RADEON_VA_RESERVED_SIZE         (8 << 20)
-#define RADEON_IB_VM_MAX_SIZE           (64 << 10)
+#define RADEON_VA_RESERVED_SIZE                 (8 << 20)
+#define RADEON_IB_VM_MAX_SIZE                   (64 << 10)
 
 /*
  * Errata workarounds.
@@ -254,8 +258,9 @@ struct radeon_fence_driver {
         uint32_t                        scratch_reg;
         uint64_t                        gpu_addr;
         volatile uint32_t               *cpu_addr;
-        atomic_t                        seq;
-        uint32_t                        last_seq;
+        /* seq is protected by ring emission lock */
+        uint64_t                        seq;
+        atomic64_t                      last_seq;
         unsigned long                   last_activity;
         wait_queue_head_t               queue;
         struct list_head                emitted;
@@ -268,11 +273,9 @@ struct radeon_fence {
         struct kref                     kref;
         struct list_head                list;
         /* protected by radeon_fence.lock */
-        uint32_t                        seq;
-        bool                            emitted;
-        bool                            signaled;
+        uint64_t                        seq;
         /* RB, DMA, etc. */
-        int                             ring;
+        unsigned                        ring;
         struct radeon_semaphore         *semaphore;
 };