diff options
author | Alex Deucher <alexander.deucher@amd.com> | 2012-09-27 15:08:35 -0400 |
---|---|---|
committer | Alex Deucher <alexander.deucher@amd.com> | 2012-12-10 16:53:23 -0500 |
commit | 4d75658bffea78f0c6f82fd46df1ec983ccacdf0 (patch) | |
tree | a6c111fe8fb7ebb76af46924ec0bc5c8f7cc961b /drivers/gpu/drm/radeon/radeon.h | |
parent | 71bfe916ebe6d026cd3d0e41c398574fc1228e03 (diff) |
drm/radeon/kms: Add initial support for async DMA on r6xx/r7xx
Uses the new multi-ring infrastucture. 6xx/7xx has a single
async DMA ring.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/radeon.h')
-rw-r--r-- | drivers/gpu/drm/radeon/radeon.h | 11 |
1 files changed, 10 insertions, 1 deletions
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h index 8c42d54c2e26..461bf53709f5 100644 --- a/drivers/gpu/drm/radeon/radeon.h +++ b/drivers/gpu/drm/radeon/radeon.h | |||
@@ -109,7 +109,7 @@ extern int radeon_lockup_timeout; | |||
109 | #define RADEON_BIOS_NUM_SCRATCH 8 | 109 | #define RADEON_BIOS_NUM_SCRATCH 8 |
110 | 110 | ||
111 | /* max number of rings */ | 111 | /* max number of rings */ |
112 | #define RADEON_NUM_RINGS 3 | 112 | #define RADEON_NUM_RINGS 4 |
113 | 113 | ||
114 | /* fence seq are set to this number when signaled */ | 114 | /* fence seq are set to this number when signaled */ |
115 | #define RADEON_FENCE_SIGNALED_SEQ 0LL | 115 | #define RADEON_FENCE_SIGNALED_SEQ 0LL |
@@ -122,6 +122,9 @@ extern int radeon_lockup_timeout; | |||
122 | #define CAYMAN_RING_TYPE_CP1_INDEX 1 | 122 | #define CAYMAN_RING_TYPE_CP1_INDEX 1 |
123 | #define CAYMAN_RING_TYPE_CP2_INDEX 2 | 123 | #define CAYMAN_RING_TYPE_CP2_INDEX 2 |
124 | 124 | ||
125 | /* R600+ has an async dma ring */ | ||
126 | #define R600_RING_TYPE_DMA_INDEX 3 | ||
127 | |||
125 | /* hardcode those limit for now */ | 128 | /* hardcode those limit for now */ |
126 | #define RADEON_VA_IB_OFFSET (1 << 20) | 129 | #define RADEON_VA_IB_OFFSET (1 << 20) |
127 | #define RADEON_VA_RESERVED_SIZE (8 << 20) | 130 | #define RADEON_VA_RESERVED_SIZE (8 << 20) |
@@ -787,6 +790,11 @@ int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigne | |||
787 | void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp); | 790 | void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp); |
788 | 791 | ||
789 | 792 | ||
793 | /* r600 async dma */ | ||
794 | void r600_dma_stop(struct radeon_device *rdev); | ||
795 | int r600_dma_resume(struct radeon_device *rdev); | ||
796 | void r600_dma_fini(struct radeon_device *rdev); | ||
797 | |||
790 | /* | 798 | /* |
791 | * CS. | 799 | * CS. |
792 | */ | 800 | */ |
@@ -883,6 +891,7 @@ struct radeon_wb { | |||
883 | #define RADEON_WB_CP_RPTR_OFFSET 1024 | 891 | #define RADEON_WB_CP_RPTR_OFFSET 1024 |
884 | #define RADEON_WB_CP1_RPTR_OFFSET 1280 | 892 | #define RADEON_WB_CP1_RPTR_OFFSET 1280 |
885 | #define RADEON_WB_CP2_RPTR_OFFSET 1536 | 893 | #define RADEON_WB_CP2_RPTR_OFFSET 1536 |
894 | #define R600_WB_DMA_RPTR_OFFSET 1792 | ||
886 | #define R600_WB_IH_WPTR_OFFSET 2048 | 895 | #define R600_WB_IH_WPTR_OFFSET 2048 |
887 | #define R600_WB_EVENT_OFFSET 3072 | 896 | #define R600_WB_EVENT_OFFSET 3072 |
888 | 897 | ||