drm/radeon/kms: fence cleanup + more reliable GPU lockup detection V4

This patch cleanup the fence code, it drops the timeout field of
fence as the time to complete each IB is unpredictable and shouldn't
be bound.

The fence cleanup lead to GPU lockup detection improvement, this
patch introduce a callback, allowing to do asic specific test for
lockup detection. In this patch the CP is use as a first indicator
of GPU lockup. If CP doesn't make progress during 1second we assume
we are facing a GPU lockup.

To avoid overhead of testing GPU lockup frequently due to fence
taking time to be signaled we query the lockup callback every
500msec. There is plenty code comment explaining the design & choise
inside the code.

This have been tested mostly on R3XX/R5XX hw, in normal running
destkop (compiz firefox, quake3 running) the lockup callback wasn't
call once (1 hour session). Also tested with forcing GPU lockup and
lockup was reported after the 1s CP activity timeout.

V2 switch to 500ms timeout so GPU lockup get call at least 2 times
   in less than 2sec.
V3 store last jiffies in fence struct so on ERESTART, EBUSY we keep
   track of how long we already wait for a given fence
V4 make sure we got up to date cp read pointer so we don't have
   false positive

Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

1 files changed, 59 insertions, 45 deletions

diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index 034218c3dbbb..a3d13c367176 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -99,6 +99,7 @@ extern int radeon_hw_i2c;
  * symbol;
  */
 #define RADEON_MAX_USEC_TIMEOUT         100000  /* 100 ms */
+#define RADEON_FENCE_JIFFIES_TIMEOUT    (HZ / 2)
 /* RADEON_IB_POOL_SIZE must be a power of 2 */
 #define RADEON_IB_POOL_SIZE             16
 #define RADEON_DEBUGFS_MAX_NUM_FILES    32
@@ -182,7 +183,8 @@ struct radeon_fence_driver {
         uint32_t                        scratch_reg;
         atomic_t                        seq;
         uint32_t                        last_seq;
-        unsigned long                   count_timeout;
+        unsigned long                   last_jiffies;
+        unsigned long                   last_timeout;
         wait_queue_head_t               queue;
         rwlock_t                        lock;
         struct list_head                created;
@@ -197,7 +199,6 @@ struct radeon_fence {
         struct list_head                list;
         /* protected by radeon_fence.lock */
         uint32_t                        seq;
-        unsigned long                   timeout;
         bool                            emited;
         bool                            signaled;
 };
@@ -746,6 +747,7 @@ struct radeon_asic {
         int (*resume)(struct radeon_device *rdev);
         int (*suspend)(struct radeon_device *rdev);
         void (*vga_set_state)(struct radeon_device *rdev, bool state);
+        bool (*gpu_is_lockup)(struct radeon_device *rdev);
         int (*gpu_reset)(struct radeon_device *rdev);
         void (*gart_tlb_flush)(struct radeon_device *rdev);
         int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr);
@@ -804,59 +806,68 @@ struct radeon_asic {
 /*
  * Asic structures
  */
+struct r100_gpu_lockup {
+        unsigned long   last_jiffies;
+        u32             last_cp_rptr;
+};
+
 struct r100_asic {
-        const unsigned  *reg_safe_bm;
-        unsigned        reg_safe_bm_size;
-        u32             hdp_cntl;
+        const unsigned          *reg_safe_bm;
+        unsigned                reg_safe_bm_size;
+        u32                     hdp_cntl;
+        struct r100_gpu_lockup  lockup;
 };
 
 struct r300_asic {
-        const unsigned  *reg_safe_bm;
-        unsigned        reg_safe_bm_size;
-        u32             resync_scratch;
-        u32             hdp_cntl;
+        const unsigned          *reg_safe_bm;
+        unsigned                reg_safe_bm_size;
+        u32                     resync_scratch;
+        u32                     hdp_cntl;
+        struct r100_gpu_lockup  lockup;
 };
 
 struct r600_asic {
-        unsigned max_pipes;
-        unsigned max_tile_pipes;
-        unsigned max_simds;
-        unsigned max_backends;
-        unsigned max_gprs;
-        unsigned max_threads;
-        unsigned max_stack_entries;
-        unsigned max_hw_contexts;
-        unsigned max_gs_threads;
-        unsigned sx_max_export_size;
-        unsigned sx_max_export_pos_size;
-        unsigned sx_max_export_smx_size;
-        unsigned sq_num_cf_insts;
-        unsigned tiling_nbanks;
-        unsigned tiling_npipes;
-        unsigned tiling_group_size;
+        unsigned                max_pipes;
+        unsigned                max_tile_pipes;
+        unsigned                max_simds;
+        unsigned                max_backends;
+        unsigned                max_gprs;
+        unsigned                max_threads;
+        unsigned                max_stack_entries;
+        unsigned                max_hw_contexts;
+        unsigned                max_gs_threads;
+        unsigned                sx_max_export_size;
+        unsigned                sx_max_export_pos_size;
+        unsigned                sx_max_export_smx_size;
+        unsigned                sq_num_cf_insts;
+        unsigned                tiling_nbanks;
+        unsigned                tiling_npipes;
+        unsigned                tiling_group_size;
+        struct r100_gpu_lockup  lockup;
 };
 
 struct rv770_asic {
-        unsigned max_pipes;
-        unsigned max_tile_pipes;
-        unsigned max_simds;
-        unsigned max_backends;
-        unsigned max_gprs;
-        unsigned max_threads;
-        unsigned max_stack_entries;
-        unsigned max_hw_contexts;
-        unsigned max_gs_threads;
-        unsigned sx_max_export_size;
-        unsigned sx_max_export_pos_size;
-        unsigned sx_max_export_smx_size;
-        unsigned sq_num_cf_insts;
-        unsigned sx_num_of_sets;
-        unsigned sc_prim_fifo_size;
-        unsigned sc_hiz_tile_fifo_size;
-        unsigned sc_earlyz_tile_fifo_fize;
-        unsigned tiling_nbanks;
-        unsigned tiling_npipes;
-        unsigned tiling_group_size;
+        unsigned                max_pipes;
+        unsigned                max_tile_pipes;
+        unsigned                max_simds;
+        unsigned                max_backends;
+        unsigned                max_gprs;
+        unsigned                max_threads;
+        unsigned                max_stack_entries;
+        unsigned                max_hw_contexts;
+        unsigned                max_gs_threads;
+        unsigned                sx_max_export_size;
+        unsigned                sx_max_export_pos_size;
+        unsigned                sx_max_export_smx_size;
+        unsigned                sq_num_cf_insts;
+        unsigned                sx_num_of_sets;
+        unsigned                sc_prim_fifo_size;
+        unsigned                sc_hiz_tile_fifo_size;
+        unsigned                sc_earlyz_tile_fifo_fize;
+        unsigned                tiling_nbanks;
+        unsigned                tiling_npipes;
+        unsigned                tiling_group_size;
+        struct r100_gpu_lockup  lockup;
 };
 
 union radeon_asic_config {
@@ -1145,6 +1156,7 @@ static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v)
 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
 #define radeon_cs_parse(p) rdev->asic->cs_parse((p))
 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
+#define radeon_gpu_is_lockup(rdev) (rdev)->asic->gpu_is_lockup((rdev))
 #define radeon_gpu_reset(rdev) (rdev)->asic->gpu_reset((rdev))
 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev))
 #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p))
@@ -1200,6 +1212,8 @@ extern int radeon_resume_kms(struct drm_device *dev);
 extern int radeon_suspend_kms(struct drm_device *dev, pm_message_t state);
 
 /* r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 */
+extern void r100_gpu_lockup_update(struct r100_gpu_lockup *lockup, struct radeon_cp *cp);
+extern bool r100_gpu_cp_is_lockup(struct radeon_device *rdev, struct r100_gpu_lockup *lockup, struct radeon_cp *cp);
 
 /* rv200,rv250,rv280 */
 extern void r200_set_safe_registers(struct radeon_device *rdev);