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authorDave Airlie <airlied@redhat.com>2009-08-12 04:43:14 -0400
committerDave Airlie <airlied@redhat.com>2009-08-15 18:36:34 -0400
commitde1b28989edff519d0548ebaa3f94fd3d1524cf2 (patch)
treeea8bed0a409ced13c31ff68c62cf89e2b4cfd8b8 /drivers/gpu/drm/radeon/radeon.h
parent7ed220d738cf16adff6bc3b31ad25b8848a2fa9c (diff)
drm/radeon/kms: cut down indirects in register accesses.
We really don't want to be doing all these indirects, updating the GPU gart table is something we do often so the less overhead the better. Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/radeon.h')
-rw-r--r--drivers/gpu/drm/radeon/radeon.h51
1 files changed, 43 insertions, 8 deletions
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index 346112740846..87170a56e37b 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -667,14 +667,11 @@ struct radeon_device {
667 resource_size_t rmmio_base; 667 resource_size_t rmmio_base;
668 resource_size_t rmmio_size; 668 resource_size_t rmmio_size;
669 void *rmmio; 669 void *rmmio;
670 radeon_rreg_t mm_rreg;
671 radeon_wreg_t mm_wreg;
672 radeon_rreg_t mc_rreg; 670 radeon_rreg_t mc_rreg;
673 radeon_wreg_t mc_wreg; 671 radeon_wreg_t mc_wreg;
674 radeon_rreg_t pll_rreg; 672 radeon_rreg_t pll_rreg;
675 radeon_wreg_t pll_wreg; 673 radeon_wreg_t pll_wreg;
676 radeon_rreg_t pcie_rreg; 674 uint32_t pcie_reg_mask;
677 radeon_wreg_t pcie_wreg;
678 radeon_rreg_t pciep_rreg; 675 radeon_rreg_t pciep_rreg;
679 radeon_wreg_t pciep_wreg; 676 radeon_wreg_t pciep_wreg;
680 struct radeon_clock clock; 677 struct radeon_clock clock;
@@ -706,22 +703,42 @@ int radeon_device_init(struct radeon_device *rdev,
706void radeon_device_fini(struct radeon_device *rdev); 703void radeon_device_fini(struct radeon_device *rdev);
707int radeon_gpu_wait_for_idle(struct radeon_device *rdev); 704int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
708 705
706static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg)
707{
708 if (reg < 0x10000)
709 return readl(((void __iomem *)rdev->rmmio) + reg);
710 else {
711 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
712 return readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
713 }
714}
715
716static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
717{
718 if (reg < 0x10000)
719 writel(v, ((void __iomem *)rdev->rmmio) + reg);
720 else {
721 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
722 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
723 }
724}
725
709 726
710/* 727/*
711 * Registers read & write functions. 728 * Registers read & write functions.
712 */ 729 */
713#define RREG8(reg) readb(((void __iomem *)rdev->rmmio) + (reg)) 730#define RREG8(reg) readb(((void __iomem *)rdev->rmmio) + (reg))
714#define WREG8(reg, v) writeb(v, ((void __iomem *)rdev->rmmio) + (reg)) 731#define WREG8(reg, v) writeb(v, ((void __iomem *)rdev->rmmio) + (reg))
715#define RREG32(reg) rdev->mm_rreg(rdev, (reg)) 732#define RREG32(reg) r100_mm_rreg(rdev, (reg))
716#define WREG32(reg, v) rdev->mm_wreg(rdev, (reg), (v)) 733#define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v))
717#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 734#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
718#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 735#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
719#define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg)) 736#define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
720#define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v)) 737#define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
721#define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg)) 738#define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
722#define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v)) 739#define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
723#define RREG32_PCIE(reg) rdev->pcie_rreg(rdev, (reg)) 740#define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
724#define WREG32_PCIE(reg, v) rdev->pcie_wreg(rdev, (reg), (v)) 741#define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
725#define WREG32_P(reg, val, mask) \ 742#define WREG32_P(reg, val, mask) \
726 do { \ 743 do { \
727 uint32_t tmp_ = RREG32(reg); \ 744 uint32_t tmp_ = RREG32(reg); \
@@ -737,6 +754,24 @@ int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
737 WREG32_PLL(reg, tmp_); \ 754 WREG32_PLL(reg, tmp_); \
738 } while (0) 755 } while (0)
739 756
757/*
758 * Indirect registers accessor
759 */
760static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
761{
762 uint32_t r;
763
764 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
765 r = RREG32(RADEON_PCIE_DATA);
766 return r;
767}
768
769static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
770{
771 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
772 WREG32(RADEON_PCIE_DATA, (v));
773}
774
740void r100_pll_errata_after_index(struct radeon_device *rdev); 775void r100_pll_errata_after_index(struct radeon_device *rdev);
741 776
742 777