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author | Linus Torvalds <torvalds@linux-foundation.org> | 2009-11-11 14:32:04 -0500 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2009-11-11 14:32:04 -0500 |
commit | 6b46362c0ea472b174c336786fd406c504326ad4 (patch) | |
tree | f403d941d88ea9e2ee59ec977cb4d6c7b782018d /drivers/gpu/drm/radeon/r600d.h | |
parent | 961767b75d63c21aa60ee3ccf940288c3c1afde6 (diff) | |
parent | eeba57518c01cf462d87bbfc59049139da47adcb (diff) |
Merge branch 'drm-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6
* 'drm-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6: (52 commits)
drm/kms: Init the CRTC info fields for modes forced from the command line.
drm/radeon/r600: CS parser updates
drm/radeon/kms: add debugfs for power management for AtomBIOS devices
drm/radeon/kms: initial mode validation support
drm/radeon/kms/atom/dce3: call transmitter init on mode set
drm/radeon/kms: store detailed connector info
drm/radeon/kms/atom/dce3: fix up usPixelClock calculation for Transmitter tables
drm/radeon/kms/r600: fix rs880 support v2
drm/radeon/kms/r700: fix some typos in chip init
drm/radeon/kms: remove some misleading debugging output
drm/radeon/kms: stop putting VRAM at 0 in MC space on r600s.
drm/radeon/kms: disable D1VGA and D2VGA if enabled
drm/radeon/kms: Don't RMW CP_RB_CNTL
drm/radeon/kms: fix coherency issues on AGP cards.
drm/radeon/kms: fix rc410 suspend/resume.
drm/radeon/kms: add quirk for hp dc5750
drm/radeon/kms/atom: fix potential oops in spread spectrum code
drm/kms: typo fix
drm/radeon/kms/atom: Make card_info per device
drm/radeon/kms/atom: Fix DVO support
...
Diffstat (limited to 'drivers/gpu/drm/radeon/r600d.h')
-rw-r--r-- | drivers/gpu/drm/radeon/r600d.h | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/r600d.h b/drivers/gpu/drm/radeon/r600d.h index 9b64d47f1f82..27ab428b149b 100644 --- a/drivers/gpu/drm/radeon/r600d.h +++ b/drivers/gpu/drm/radeon/r600d.h | |||
@@ -119,6 +119,7 @@ | |||
119 | #define DB_DEBUG 0x9830 | 119 | #define DB_DEBUG 0x9830 |
120 | #define PREZ_MUST_WAIT_FOR_POSTZ_DONE (1 << 31) | 120 | #define PREZ_MUST_WAIT_FOR_POSTZ_DONE (1 << 31) |
121 | #define DB_DEPTH_BASE 0x2800C | 121 | #define DB_DEPTH_BASE 0x2800C |
122 | #define DB_HTILE_DATA_BASE 0x28014 | ||
122 | #define DB_WATERMARKS 0x9838 | 123 | #define DB_WATERMARKS 0x9838 |
123 | #define DEPTH_FREE(x) ((x) << 0) | 124 | #define DEPTH_FREE(x) ((x) << 0) |
124 | #define DEPTH_FLUSH(x) ((x) << 5) | 125 | #define DEPTH_FLUSH(x) ((x) << 5) |
@@ -171,6 +172,14 @@ | |||
171 | #define SQ_STACK_RESOURCE_MGMT_2 0x8c14 | 172 | #define SQ_STACK_RESOURCE_MGMT_2 0x8c14 |
172 | # define NUM_GS_STACK_ENTRIES(x) ((x) << 0) | 173 | # define NUM_GS_STACK_ENTRIES(x) ((x) << 0) |
173 | # define NUM_ES_STACK_ENTRIES(x) ((x) << 16) | 174 | # define NUM_ES_STACK_ENTRIES(x) ((x) << 16) |
175 | #define SQ_ESGS_RING_BASE 0x8c40 | ||
176 | #define SQ_GSVS_RING_BASE 0x8c48 | ||
177 | #define SQ_ESTMP_RING_BASE 0x8c50 | ||
178 | #define SQ_GSTMP_RING_BASE 0x8c58 | ||
179 | #define SQ_VSTMP_RING_BASE 0x8c60 | ||
180 | #define SQ_PSTMP_RING_BASE 0x8c68 | ||
181 | #define SQ_FBUF_RING_BASE 0x8c70 | ||
182 | #define SQ_REDUC_RING_BASE 0x8c78 | ||
174 | 183 | ||
175 | #define GRBM_CNTL 0x8000 | 184 | #define GRBM_CNTL 0x8000 |
176 | # define GRBM_READ_TIMEOUT(x) ((x) << 0) | 185 | # define GRBM_READ_TIMEOUT(x) ((x) << 0) |
@@ -271,6 +280,10 @@ | |||
271 | #define PCIE_PORT_INDEX 0x0038 | 280 | #define PCIE_PORT_INDEX 0x0038 |
272 | #define PCIE_PORT_DATA 0x003C | 281 | #define PCIE_PORT_DATA 0x003C |
273 | 282 | ||
283 | #define CHMAP 0x2004 | ||
284 | #define NOOFCHAN_SHIFT 12 | ||
285 | #define NOOFCHAN_MASK 0x00003000 | ||
286 | |||
274 | #define RAMCFG 0x2408 | 287 | #define RAMCFG 0x2408 |
275 | #define NOOFBANK_SHIFT 0 | 288 | #define NOOFBANK_SHIFT 0 |
276 | #define NOOFBANK_MASK 0x00000001 | 289 | #define NOOFBANK_MASK 0x00000001 |
@@ -352,6 +365,7 @@ | |||
352 | 365 | ||
353 | 366 | ||
354 | #define SX_MISC 0x28350 | 367 | #define SX_MISC 0x28350 |
368 | #define SX_MEMORY_EXPORT_BASE 0x9010 | ||
355 | #define SX_DEBUG_1 0x9054 | 369 | #define SX_DEBUG_1 0x9054 |
356 | #define SMX_EVENT_RELEASE (1 << 0) | 370 | #define SMX_EVENT_RELEASE (1 << 0) |
357 | #define ENABLE_NEW_SMX_ADDRESS (1 << 16) | 371 | #define ENABLE_NEW_SMX_ADDRESS (1 << 16) |