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authorShawn Guo <shawn.guo@linaro.org>2012-09-17 03:10:58 -0400
committerShawn Guo <shawn.guo@linaro.org>2012-09-17 03:10:58 -0400
commit8f71fb87e288c5f374ea0e0ddac18707b6649f72 (patch)
treedd77032ddcfcfe995436031281eb008a471cfc30 /drivers/gpu/drm/radeon/r600d.h
parentd9875690d9b89a866022ff49e3fcea892345ad92 (diff)
parentf8135a74df53ba7010a162dddd112b73ee5652e3 (diff)
Merge tag 'imx-dt-3.7' into imx/dt-for-3.7-2
Diffstat (limited to 'drivers/gpu/drm/radeon/r600d.h')
-rw-r--r--drivers/gpu/drm/radeon/r600d.h17
1 files changed, 17 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/r600d.h b/drivers/gpu/drm/radeon/r600d.h
index fd328f4c3ea8..bdb69a63062f 100644
--- a/drivers/gpu/drm/radeon/r600d.h
+++ b/drivers/gpu/drm/radeon/r600d.h
@@ -92,6 +92,20 @@
92#define R_028094_CB_COLOR5_VIEW 0x028094 92#define R_028094_CB_COLOR5_VIEW 0x028094
93#define R_028098_CB_COLOR6_VIEW 0x028098 93#define R_028098_CB_COLOR6_VIEW 0x028098
94#define R_02809C_CB_COLOR7_VIEW 0x02809C 94#define R_02809C_CB_COLOR7_VIEW 0x02809C
95#define R_028100_CB_COLOR0_MASK 0x028100
96#define S_028100_CMASK_BLOCK_MAX(x) (((x) & 0xFFF) << 0)
97#define G_028100_CMASK_BLOCK_MAX(x) (((x) >> 0) & 0xFFF)
98#define C_028100_CMASK_BLOCK_MAX 0xFFFFF000
99#define S_028100_FMASK_TILE_MAX(x) (((x) & 0xFFFFF) << 12)
100#define G_028100_FMASK_TILE_MAX(x) (((x) >> 12) & 0xFFFFF)
101#define C_028100_FMASK_TILE_MAX 0x00000FFF
102#define R_028104_CB_COLOR1_MASK 0x028104
103#define R_028108_CB_COLOR2_MASK 0x028108
104#define R_02810C_CB_COLOR3_MASK 0x02810C
105#define R_028110_CB_COLOR4_MASK 0x028110
106#define R_028114_CB_COLOR5_MASK 0x028114
107#define R_028118_CB_COLOR6_MASK 0x028118
108#define R_02811C_CB_COLOR7_MASK 0x02811C
95#define CB_COLOR0_INFO 0x280a0 109#define CB_COLOR0_INFO 0x280a0
96# define CB_FORMAT(x) ((x) << 2) 110# define CB_FORMAT(x) ((x) << 2)
97# define CB_ARRAY_MODE(x) ((x) << 8) 111# define CB_ARRAY_MODE(x) ((x) << 8)
@@ -1400,6 +1414,9 @@
1400#define S_0280A0_TILE_MODE(x) (((x) & 0x3) << 18) 1414#define S_0280A0_TILE_MODE(x) (((x) & 0x3) << 18)
1401#define G_0280A0_TILE_MODE(x) (((x) >> 18) & 0x3) 1415#define G_0280A0_TILE_MODE(x) (((x) >> 18) & 0x3)
1402#define C_0280A0_TILE_MODE 0xFFF3FFFF 1416#define C_0280A0_TILE_MODE 0xFFF3FFFF
1417#define V_0280A0_TILE_DISABLE 0
1418#define V_0280A0_CLEAR_ENABLE 1
1419#define V_0280A0_FRAG_ENABLE 2
1403#define S_0280A0_BLEND_CLAMP(x) (((x) & 0x1) << 20) 1420#define S_0280A0_BLEND_CLAMP(x) (((x) & 0x1) << 20)
1404#define G_0280A0_BLEND_CLAMP(x) (((x) >> 20) & 0x1) 1421#define G_0280A0_BLEND_CLAMP(x) (((x) >> 20) & 0x1)
1405#define C_0280A0_BLEND_CLAMP 0xFFEFFFFF 1422#define C_0280A0_BLEND_CLAMP 0xFFEFFFFF