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authorRafał Miłecki <zajec5@gmail.com>2011-12-24 06:25:36 -0500
committerDave Airlie <airlied@redhat.com>2012-01-03 04:40:47 -0500
commit93a4ed878a22b8489723bc3ab89dd401128bbc9e (patch)
treeffd74a39863414c98439ed75e658a07cdcc2b3f4 /drivers/gpu/drm/radeon/r600_hdmi.c
parent92db7f6c860b8190571a9dc1fcbc16d003422fe8 (diff)
drm/radeon/kms: define TMDS/LVTM HDMI enabling bits
The names has been taken from free M76 specs. Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Reviewed-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/r600_hdmi.c')
-rw-r--r--drivers/gpu/drm/radeon/r600_hdmi.c12
1 files changed, 8 insertions, 4 deletions
diff --git a/drivers/gpu/drm/radeon/r600_hdmi.c b/drivers/gpu/drm/radeon/r600_hdmi.c
index 2c70a85e72c6..0b5920671450 100644
--- a/drivers/gpu/drm/radeon/r600_hdmi.c
+++ b/drivers/gpu/drm/radeon/r600_hdmi.c
@@ -533,11 +533,13 @@ void r600_hdmi_enable(struct drm_encoder *encoder)
533 } else if (rdev->family >= CHIP_R600) { 533 } else if (rdev->family >= CHIP_R600) {
534 switch (radeon_encoder->encoder_id) { 534 switch (radeon_encoder->encoder_id) {
535 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 535 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
536 WREG32_P(AVIVO_TMDSA_CNTL, 0x4, ~0x4); 536 WREG32_P(AVIVO_TMDSA_CNTL, AVIVO_TMDSA_CNTL_HDMI_EN,
537 ~AVIVO_TMDSA_CNTL_HDMI_EN);
537 WREG32(offset + R600_HDMI_ENABLE, 0x101); 538 WREG32(offset + R600_HDMI_ENABLE, 0x101);
538 break; 539 break;
539 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 540 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
540 WREG32_P(AVIVO_LVTMA_CNTL, 0x4, ~0x4); 541 WREG32_P(AVIVO_LVTMA_CNTL, AVIVO_LVTMA_CNTL_HDMI_EN,
542 ~AVIVO_LVTMA_CNTL_HDMI_EN);
541 WREG32(offset + R600_HDMI_ENABLE, 0x105); 543 WREG32(offset + R600_HDMI_ENABLE, 0x105);
542 break; 544 break;
543 default: 545 default:
@@ -603,11 +605,13 @@ void r600_hdmi_disable(struct drm_encoder *encoder)
603 } else if (rdev->family >= CHIP_R600 && !ASIC_IS_DCE3(rdev)) { 605 } else if (rdev->family >= CHIP_R600 && !ASIC_IS_DCE3(rdev)) {
604 switch (radeon_encoder->encoder_id) { 606 switch (radeon_encoder->encoder_id) {
605 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 607 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
606 WREG32_P(AVIVO_TMDSA_CNTL, 0, ~0x4); 608 WREG32_P(AVIVO_TMDSA_CNTL, 0,
609 ~AVIVO_TMDSA_CNTL_HDMI_EN);
607 WREG32(offset + R600_HDMI_ENABLE, 0); 610 WREG32(offset + R600_HDMI_ENABLE, 0);
608 break; 611 break;
609 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 612 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
610 WREG32_P(AVIVO_LVTMA_CNTL, 0, ~0x4); 613 WREG32_P(AVIVO_LVTMA_CNTL, 0,
614 ~AVIVO_LVTMA_CNTL_HDMI_EN);
611 WREG32(offset + R600_HDMI_ENABLE, 0); 615 WREG32(offset + R600_HDMI_ENABLE, 0);
612 break; 616 break;
613 default: 617 default: