diff options
author | Alex Deucher <alexander.deucher@amd.com> | 2013-05-09 17:14:11 -0400 |
---|---|---|
committer | Alex Deucher <alexander.deucher@amd.com> | 2013-08-30 16:30:22 -0400 |
commit | 018042b15b556807afd0393b285f001fce515151 (patch) | |
tree | 3a50f222dc19676acf909d86123a4102bfe35529 /drivers/gpu/drm/radeon/r600_dpm.c | |
parent | 57ff476171f4065ab0312be0752f3439ee943ebe (diff) |
drm/radeon: parse the uvd clock voltage deps table
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/r600_dpm.c')
-rw-r--r-- | drivers/gpu/drm/radeon/r600_dpm.c | 40 |
1 files changed, 40 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/r600_dpm.c b/drivers/gpu/drm/radeon/r600_dpm.c index b49b0f0795f0..c103d3fd9428 100644 --- a/drivers/gpu/drm/radeon/r600_dpm.c +++ b/drivers/gpu/drm/radeon/r600_dpm.c | |||
@@ -1030,6 +1030,42 @@ int r600_parse_extended_power_table(struct radeon_device *rdev) | |||
1030 | le16_to_cpu(limits->entries[i].usVoltage); | 1030 | le16_to_cpu(limits->entries[i].usVoltage); |
1031 | } | 1031 | } |
1032 | } | 1032 | } |
1033 | if ((le16_to_cpu(ext_hdr->usSize) >= SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V3) && | ||
1034 | ext_hdr->usUVDTableOffset) { | ||
1035 | UVDClockInfoArray *array = (UVDClockInfoArray *) | ||
1036 | (mode_info->atom_context->bios + data_offset + | ||
1037 | le16_to_cpu(ext_hdr->usUVDTableOffset) + 1); | ||
1038 | ATOM_PPLIB_UVD_Clock_Voltage_Limit_Table *limits = | ||
1039 | (ATOM_PPLIB_UVD_Clock_Voltage_Limit_Table *) | ||
1040 | (mode_info->atom_context->bios + data_offset + | ||
1041 | le16_to_cpu(ext_hdr->usUVDTableOffset) + 1 + | ||
1042 | 1 + (array->ucNumEntries * sizeof (UVDClockInfo))); | ||
1043 | u32 size = limits->numEntries * | ||
1044 | sizeof(struct radeon_uvd_clock_voltage_dependency_entry); | ||
1045 | rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries = | ||
1046 | kzalloc(size, GFP_KERNEL); | ||
1047 | if (!rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries) { | ||
1048 | kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries); | ||
1049 | kfree(rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk.entries); | ||
1050 | kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries); | ||
1051 | kfree(rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.entries); | ||
1052 | kfree(rdev->pm.dpm.dyn_state.cac_leakage_table.entries); | ||
1053 | kfree(rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries); | ||
1054 | return -ENOMEM; | ||
1055 | } | ||
1056 | rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count = | ||
1057 | limits->numEntries; | ||
1058 | for (i = 0; i < limits->numEntries; i++) { | ||
1059 | UVDClockInfo *uvd_clk = | ||
1060 | &array->entries[limits->entries[i].ucUVDClockInfoIndex]; | ||
1061 | rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[i].vclk = | ||
1062 | le16_to_cpu(uvd_clk->usVClkLow) | (uvd_clk->ucVClkHigh << 16); | ||
1063 | rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[i].dclk = | ||
1064 | le16_to_cpu(uvd_clk->usDClkLow) | (uvd_clk->ucDClkHigh << 16); | ||
1065 | rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[i].v = | ||
1066 | le16_to_cpu(limits->entries[i].usVoltage); | ||
1067 | } | ||
1068 | } | ||
1033 | if ((le16_to_cpu(ext_hdr->usSize) >= SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V5) && | 1069 | if ((le16_to_cpu(ext_hdr->usSize) >= SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V5) && |
1034 | ext_hdr->usPPMTableOffset) { | 1070 | ext_hdr->usPPMTableOffset) { |
1035 | ATOM_PPLIB_PPM_Table *ppm = (ATOM_PPLIB_PPM_Table *) | 1071 | ATOM_PPLIB_PPM_Table *ppm = (ATOM_PPLIB_PPM_Table *) |
@@ -1044,6 +1080,7 @@ int r600_parse_extended_power_table(struct radeon_device *rdev) | |||
1044 | kfree(rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.entries); | 1080 | kfree(rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.entries); |
1045 | kfree(rdev->pm.dpm.dyn_state.cac_leakage_table.entries); | 1081 | kfree(rdev->pm.dpm.dyn_state.cac_leakage_table.entries); |
1046 | kfree(rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries); | 1082 | kfree(rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries); |
1083 | kfree(rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries); | ||
1047 | return -ENOMEM; | 1084 | return -ENOMEM; |
1048 | } | 1085 | } |
1049 | rdev->pm.dpm.dyn_state.ppm_table->ppm_design = ppm->ucPpmDesign; | 1086 | rdev->pm.dpm.dyn_state.ppm_table->ppm_design = ppm->ucPpmDesign; |
@@ -1081,6 +1118,7 @@ int r600_parse_extended_power_table(struct radeon_device *rdev) | |||
1081 | kfree(rdev->pm.dpm.dyn_state.cac_leakage_table.entries); | 1118 | kfree(rdev->pm.dpm.dyn_state.cac_leakage_table.entries); |
1082 | kfree(rdev->pm.dpm.dyn_state.ppm_table); | 1119 | kfree(rdev->pm.dpm.dyn_state.ppm_table); |
1083 | kfree(rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries); | 1120 | kfree(rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries); |
1121 | kfree(rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries); | ||
1084 | return -ENOMEM; | 1122 | return -ENOMEM; |
1085 | } | 1123 | } |
1086 | if (rev > 0) { | 1124 | if (rev > 0) { |
@@ -1135,6 +1173,8 @@ void r600_free_extended_power_table(struct radeon_device *rdev) | |||
1135 | kfree(rdev->pm.dpm.dyn_state.cac_tdp_table); | 1173 | kfree(rdev->pm.dpm.dyn_state.cac_tdp_table); |
1136 | if (rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries) | 1174 | if (rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries) |
1137 | kfree(rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries); | 1175 | kfree(rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries); |
1176 | if (rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries) | ||
1177 | kfree(rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries); | ||
1138 | } | 1178 | } |
1139 | 1179 | ||
1140 | enum radeon_pcie_gen r600_get_pcie_gen_support(struct radeon_device *rdev, | 1180 | enum radeon_pcie_gen r600_get_pcie_gen_support(struct radeon_device *rdev, |