diff options
author | Alex Deucher <alexander.deucher@amd.com> | 2014-10-13 13:20:02 -0400 |
---|---|---|
committer | Alex Deucher <alexander.deucher@amd.com> | 2014-10-16 18:34:07 -0400 |
commit | adfed2b0587289013f8143c54913ddfd44ac1fd3 (patch) | |
tree | 738a650b2b3c88d3a8c5b25315cafa42a1874720 /drivers/gpu/drm/radeon/r600_dma.c | |
parent | 4910403836ded89803fab201d4b5caaa85de3a89 (diff) |
drm/radeon: use gart memory for DMA ring tests
Avoids HDP cache flush issues when using vram which can
cause ring test failures on certain boards.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: Alexander Fyodorov <halcy@yandex.ru>
Cc: stable@vger.kernel.org
Diffstat (limited to 'drivers/gpu/drm/radeon/r600_dma.c')
-rw-r--r-- | drivers/gpu/drm/radeon/r600_dma.c | 21 |
1 files changed, 12 insertions, 9 deletions
diff --git a/drivers/gpu/drm/radeon/r600_dma.c b/drivers/gpu/drm/radeon/r600_dma.c index a49db830a47f..d9375a361985 100644 --- a/drivers/gpu/drm/radeon/r600_dma.c +++ b/drivers/gpu/drm/radeon/r600_dma.c | |||
@@ -241,16 +241,19 @@ int r600_dma_ring_test(struct radeon_device *rdev, | |||
241 | { | 241 | { |
242 | unsigned i; | 242 | unsigned i; |
243 | int r; | 243 | int r; |
244 | void __iomem *ptr = (void *)rdev->vram_scratch.ptr; | 244 | unsigned index; |
245 | u32 tmp; | 245 | u32 tmp; |
246 | u64 gpu_addr; | ||
246 | 247 | ||
247 | if (!ptr) { | 248 | if (ring->idx == R600_RING_TYPE_DMA_INDEX) |
248 | DRM_ERROR("invalid vram scratch pointer\n"); | 249 | index = R600_WB_DMA_RING_TEST_OFFSET; |
249 | return -EINVAL; | 250 | else |
250 | } | 251 | index = CAYMAN_WB_DMA1_RING_TEST_OFFSET; |
252 | |||
253 | gpu_addr = rdev->wb.gpu_addr + index; | ||
251 | 254 | ||
252 | tmp = 0xCAFEDEAD; | 255 | tmp = 0xCAFEDEAD; |
253 | writel(tmp, ptr); | 256 | rdev->wb.wb[index/4] = cpu_to_le32(tmp); |
254 | 257 | ||
255 | r = radeon_ring_lock(rdev, ring, 4); | 258 | r = radeon_ring_lock(rdev, ring, 4); |
256 | if (r) { | 259 | if (r) { |
@@ -258,13 +261,13 @@ int r600_dma_ring_test(struct radeon_device *rdev, | |||
258 | return r; | 261 | return r; |
259 | } | 262 | } |
260 | radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1)); | 263 | radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1)); |
261 | radeon_ring_write(ring, rdev->vram_scratch.gpu_addr & 0xfffffffc); | 264 | radeon_ring_write(ring, lower_32_bits(gpu_addr)); |
262 | radeon_ring_write(ring, upper_32_bits(rdev->vram_scratch.gpu_addr) & 0xff); | 265 | radeon_ring_write(ring, upper_32_bits(gpu_addr) & 0xff); |
263 | radeon_ring_write(ring, 0xDEADBEEF); | 266 | radeon_ring_write(ring, 0xDEADBEEF); |
264 | radeon_ring_unlock_commit(rdev, ring, false); | 267 | radeon_ring_unlock_commit(rdev, ring, false); |
265 | 268 | ||
266 | for (i = 0; i < rdev->usec_timeout; i++) { | 269 | for (i = 0; i < rdev->usec_timeout; i++) { |
267 | tmp = readl(ptr); | 270 | tmp = le32_to_cpu(rdev->wb.wb[index/4]); |
268 | if (tmp == 0xDEADBEEF) | 271 | if (tmp == 0xDEADBEEF) |
269 | break; | 272 | break; |
270 | DRM_UDELAY(1); | 273 | DRM_UDELAY(1); |