drm/radeon: 6xx/7xx non-kms endian fixes

agd5f: minor cleanups

Signed-off-by: Cédric Cano <ccano@interfaceconcept.com>
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

1 files changed, 24 insertions, 7 deletions

diff --git a/drivers/gpu/drm/radeon/r600_cp.c b/drivers/gpu/drm/radeon/r600_cp.c
index 4f4cd8b286d5..c3ab959bdc7c 100644
--- a/drivers/gpu/drm/radeon/r600_cp.c
+++ b/drivers/gpu/drm/radeon/r600_cp.c
@@ -396,6 +396,9 @@ static void r600_cp_load_microcode(drm_radeon_private_t *dev_priv)
         r600_do_cp_stop(dev_priv);
 
         RADEON_WRITE(R600_CP_RB_CNTL,
+#ifdef __BIG_ENDIAN
+                     R600_BUF_SWAP_32BIT |
+#endif
                      R600_RB_NO_UPDATE |
                      R600_RB_BLKSZ(15) |
                      R600_RB_BUFSZ(3));
@@ -486,9 +489,12 @@ static void r700_cp_load_microcode(drm_radeon_private_t *dev_priv)
         r600_do_cp_stop(dev_priv);
 
         RADEON_WRITE(R600_CP_RB_CNTL,
+#ifdef __BIG_ENDIAN
+                     R600_BUF_SWAP_32BIT |
+#endif
                      R600_RB_NO_UPDATE |
-                     (15 << 8) |
-                     (3 << 0));
+                     R600_RB_BLKSZ(15) |
+                     R600_RB_BUFSZ(3));
 
         RADEON_WRITE(R600_GRBM_SOFT_RESET, R600_SOFT_RESET_CP);
         RADEON_READ(R600_GRBM_SOFT_RESET);
@@ -550,8 +556,12 @@ static void r600_test_writeback(drm_radeon_private_t *dev_priv)
 
         if (!dev_priv->writeback_works) {
                 /* Disable writeback to avoid unnecessary bus master transfer */
-                RADEON_WRITE(R600_CP_RB_CNTL, RADEON_READ(R600_CP_RB_CNTL) |
-                             RADEON_RB_NO_UPDATE);
+                RADEON_WRITE(R600_CP_RB_CNTL,
+#ifdef __BIG_ENDIAN
+                             R600_BUF_SWAP_32BIT |
+#endif
+                             RADEON_READ(R600_CP_RB_CNTL) |
+                             R600_RB_NO_UPDATE);
                 RADEON_WRITE(R600_SCRATCH_UMSK, 0);
         }
 }
@@ -575,7 +585,11 @@ int r600_do_engine_reset(struct drm_device *dev)
 
         RADEON_WRITE(R600_CP_RB_WPTR_DELAY, 0);
         cp_rb_cntl = RADEON_READ(R600_CP_RB_CNTL);
-        RADEON_WRITE(R600_CP_RB_CNTL, R600_RB_RPTR_WR_ENA);
+        RADEON_WRITE(R600_CP_RB_CNTL,
+#ifdef __BIG_ENDIAN
+                     R600_BUF_SWAP_32BIT |
+#endif
+                     R600_RB_RPTR_WR_ENA);
 
         RADEON_WRITE(R600_CP_RB_RPTR_WR, cp_ptr);
         RADEON_WRITE(R600_CP_RB_WPTR, cp_ptr);
@@ -1838,7 +1852,10 @@ static void r600_cp_init_ring_buffer(struct drm_device *dev,
                         + dev_priv->gart_vm_start;
         }
         RADEON_WRITE(R600_CP_RB_RPTR_ADDR,
-                     rptr_addr & 0xffffffff);
+#ifdef __BIG_ENDIAN
+                     (2 << 0) |
+#endif
+                     (rptr_addr & 0xfffffffc));
         RADEON_WRITE(R600_CP_RB_RPTR_ADDR_HI,
                      upper_32_bits(rptr_addr));
 
@@ -1889,7 +1906,7 @@ static void r600_cp_init_ring_buffer(struct drm_device *dev,
         {
                 u64 scratch_addr;
 
-                scratch_addr = RADEON_READ(R600_CP_RB_RPTR_ADDR);
+                scratch_addr = RADEON_READ(R600_CP_RB_RPTR_ADDR) & 0xFFFFFFFC;
                 scratch_addr |= ((u64)RADEON_READ(R600_CP_RB_RPTR_ADDR_HI)) << 32;
                 scratch_addr += R600_SCRATCH_REG_OFFSET;
                 scratch_addr >>= 8;