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authorAlex Deucher <alexdeucher@gmail.com>2009-09-09 16:09:36 -0400
committerDave Airlie <airlied@redhat.com>2009-09-09 16:53:17 -0400
commit5d93b135fc051be3740cbe55729fc7b86a7069d7 (patch)
tree2d8e49a0e609cfa3693c88d06747ef0ef2c12962 /drivers/gpu/drm/radeon/r600_blit.c
parentcecc6b63a5de547a345c491bb4c18c01a15984a4 (diff)
drm/radeon/r600: fix legacy blit code
ARRAY_SIZE is number of elements not bytes. Fix ring counts accordingly, also make a few functions static. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/r600_blit.c')
-rw-r--r--drivers/gpu/drm/radeon/r600_blit.c29
1 files changed, 12 insertions, 17 deletions
diff --git a/drivers/gpu/drm/radeon/r600_blit.c b/drivers/gpu/drm/radeon/r600_blit.c
index c51402e92493..dde2ccbf1d15 100644
--- a/drivers/gpu/drm/radeon/r600_blit.c
+++ b/drivers/gpu/drm/radeon/r600_blit.c
@@ -126,7 +126,7 @@ set_shaders(struct drm_device *dev)
126{ 126{
127 drm_radeon_private_t *dev_priv = dev->dev_private; 127 drm_radeon_private_t *dev_priv = dev->dev_private;
128 u64 gpu_addr; 128 u64 gpu_addr;
129 int shader_size, i; 129 int i;
130 u32 *vs, *ps; 130 u32 *vs, *ps;
131 uint32_t sq_pgm_resources; 131 uint32_t sq_pgm_resources;
132 RING_LOCALS; 132 RING_LOCALS;
@@ -136,11 +136,9 @@ set_shaders(struct drm_device *dev)
136 vs = (u32 *) ((char *)dev->agp_buffer_map->handle + dev_priv->blit_vb->offset); 136 vs = (u32 *) ((char *)dev->agp_buffer_map->handle + dev_priv->blit_vb->offset);
137 ps = (u32 *) ((char *)dev->agp_buffer_map->handle + dev_priv->blit_vb->offset + 256); 137 ps = (u32 *) ((char *)dev->agp_buffer_map->handle + dev_priv->blit_vb->offset + 256);
138 138
139 shader_size = r6xx_vs_size; 139 for (i = 0; i < r6xx_vs_size; i++)
140 for (i = 0; i < shader_size; i++)
141 vs[i] = r6xx_vs[i]; 140 vs[i] = r6xx_vs[i];
142 shader_size = r6xx_ps_size; 141 for (i = 0; i < r6xx_ps_size; i++)
143 for (i = 0; i < shader_size; i++)
144 ps[i] = r6xx_ps[i]; 142 ps[i] = r6xx_ps[i];
145 143
146 dev_priv->blit_vb->used = 512; 144 dev_priv->blit_vb->used = 512;
@@ -309,7 +307,7 @@ draw_auto(drm_radeon_private_t *dev_priv)
309static inline void 307static inline void
310set_default_state(drm_radeon_private_t *dev_priv) 308set_default_state(drm_radeon_private_t *dev_priv)
311{ 309{
312 int default_state_dw, i; 310 int i;
313 u32 sq_config, sq_gpr_resource_mgmt_1, sq_gpr_resource_mgmt_2; 311 u32 sq_config, sq_gpr_resource_mgmt_1, sq_gpr_resource_mgmt_2;
314 u32 sq_thread_resource_mgmt, sq_stack_resource_mgmt_1, sq_stack_resource_mgmt_2; 312 u32 sq_thread_resource_mgmt, sq_stack_resource_mgmt_1, sq_stack_resource_mgmt_2;
315 int num_ps_gprs, num_vs_gprs, num_temp_gprs, num_gs_gprs, num_es_gprs; 313 int num_ps_gprs, num_vs_gprs, num_temp_gprs, num_gs_gprs, num_es_gprs;
@@ -462,14 +460,12 @@ set_default_state(drm_radeon_private_t *dev_priv)
462 R600_NUM_ES_STACK_ENTRIES(num_es_stack_entries)); 460 R600_NUM_ES_STACK_ENTRIES(num_es_stack_entries));
463 461
464 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) { 462 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) {
465 default_state_dw = r7xx_default_size * 4; 463 BEGIN_RING(r7xx_default_size + 10);
466 BEGIN_RING(default_state_dw + 10); 464 for (i = 0; i < r7xx_default_size; i++)
467 for (i = 0; i < default_state_dw; i++)
468 OUT_RING(r7xx_default_state[i]); 465 OUT_RING(r7xx_default_state[i]);
469 } else { 466 } else {
470 default_state_dw = r6xx_default_size * 4; 467 BEGIN_RING(r6xx_default_size + 10);
471 BEGIN_RING(default_state_dw + 10); 468 for (i = 0; i < r6xx_default_size; i++)
472 for (i = 0; i < default_state_dw; i++)
473 OUT_RING(r6xx_default_state[i]); 469 OUT_RING(r6xx_default_state[i]);
474 } 470 }
475 OUT_RING(CP_PACKET3(R600_IT_EVENT_WRITE, 0)); 471 OUT_RING(CP_PACKET3(R600_IT_EVENT_WRITE, 0));
@@ -512,7 +508,7 @@ static inline uint32_t i2f(uint32_t input)
512} 508}
513 509
514 510
515int r600_nomm_get_vb(struct drm_device *dev) 511static inline int r600_nomm_get_vb(struct drm_device *dev)
516{ 512{
517 drm_radeon_private_t *dev_priv = dev->dev_private; 513 drm_radeon_private_t *dev_priv = dev->dev_private;
518 dev_priv->blit_vb = radeon_freelist_get(dev); 514 dev_priv->blit_vb = radeon_freelist_get(dev);
@@ -523,7 +519,7 @@ int r600_nomm_get_vb(struct drm_device *dev)
523 return 0; 519 return 0;
524} 520}
525 521
526void r600_nomm_put_vb(struct drm_device *dev) 522static inline void r600_nomm_put_vb(struct drm_device *dev)
527{ 523{
528 drm_radeon_private_t *dev_priv = dev->dev_private; 524 drm_radeon_private_t *dev_priv = dev->dev_private;
529 525
@@ -531,7 +527,7 @@ void r600_nomm_put_vb(struct drm_device *dev)
531 radeon_cp_discard_buffer(dev, dev_priv->blit_vb->file_priv->master, dev_priv->blit_vb); 527 radeon_cp_discard_buffer(dev, dev_priv->blit_vb->file_priv->master, dev_priv->blit_vb);
532} 528}
533 529
534void *r600_nomm_get_vb_ptr(struct drm_device *dev) 530static inline void *r600_nomm_get_vb_ptr(struct drm_device *dev)
535{ 531{
536 drm_radeon_private_t *dev_priv = dev->dev_private; 532 drm_radeon_private_t *dev_priv = dev->dev_private;
537 return (((char *)dev->agp_buffer_map->handle + 533 return (((char *)dev->agp_buffer_map->handle +
@@ -781,8 +777,7 @@ r600_blit_swap(struct drm_device *dev,
781 u64 vb_addr; 777 u64 vb_addr;
782 u32 *vb; 778 u32 *vb;
783 779
784 vb = (u32 *) ((char *)dev->agp_buffer_map->handle + 780 vb = r600_nomm_get_vb_ptr(dev);
785 dev_priv->blit_vb->offset + dev_priv->blit_vb->used);
786 781
787 if ((dev_priv->blit_vb->used + 48) > dev_priv->blit_vb->total) { 782 if ((dev_priv->blit_vb->used + 48) > dev_priv->blit_vb->total) {
788 783