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authorAlex Deucher <alexdeucher@gmail.com>2009-11-02 16:01:27 -0500
committerDave Airlie <airlied@redhat.com>2009-11-03 18:53:25 -0500
commitd6f28938d9426d12eea1578949f1d73d24ad37ec (patch)
tree5450e0a9c108ec9d5875679ece20faa770c44310 /drivers/gpu/drm/radeon/r600.c
parentdf67bed92fa86ef926da8b62a6da68722388ff72 (diff)
drm/radeon/kms: Don't RMW CP_RB_CNTL
Immediate readback seems faulty on some chips. I suspect it takes a while to get through the fifo to the actual register backbone. There's no need to read it back, so, just write the driver's copy of the register's value directly. Should fix bug 24535 and possibly 24218 Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/r600.c')
-rw-r--r--drivers/gpu/drm/radeon/r600.c8
1 files changed, 3 insertions, 5 deletions
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index e87475c87d52..60fbb236edfd 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -1272,19 +1272,17 @@ int r600_cp_resume(struct radeon_device *rdev)
1272 1272
1273 /* Set ring buffer size */ 1273 /* Set ring buffer size */
1274 rb_bufsz = drm_order(rdev->cp.ring_size / 8); 1274 rb_bufsz = drm_order(rdev->cp.ring_size / 8);
1275 tmp = RB_NO_UPDATE | (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
1275#ifdef __BIG_ENDIAN 1276#ifdef __BIG_ENDIAN
1276 WREG32(CP_RB_CNTL, BUF_SWAP_32BIT | RB_NO_UPDATE | 1277 tmp |= BUF_SWAP_32BIT;
1277 (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz);
1278#else
1279 WREG32(CP_RB_CNTL, RB_NO_UPDATE | (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz);
1280#endif 1278#endif
1279 WREG32(CP_RB_CNTL, tmp);
1281 WREG32(CP_SEM_WAIT_TIMER, 0x4); 1280 WREG32(CP_SEM_WAIT_TIMER, 0x4);
1282 1281
1283 /* Set the write pointer delay */ 1282 /* Set the write pointer delay */
1284 WREG32(CP_RB_WPTR_DELAY, 0); 1283 WREG32(CP_RB_WPTR_DELAY, 0);
1285 1284
1286 /* Initialize the ring buffer's read and write pointers */ 1285 /* Initialize the ring buffer's read and write pointers */
1287 tmp = RREG32(CP_RB_CNTL);
1288 WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA); 1286 WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
1289 WREG32(CP_RB_RPTR_WR, 0); 1287 WREG32(CP_RB_RPTR_WR, 0);
1290 WREG32(CP_RB_WPTR, 0); 1288 WREG32(CP_RB_WPTR, 0);