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authorJerome Glisse <jglisse@redhat.com>2009-10-06 13:04:30 -0400
committerDave Airlie <airlied@redhat.com>2009-10-07 19:40:04 -0400
commit1a029b768f9d4a001501bd18d6ba08297ae912fd (patch)
tree0ac1643be0d57e919a619c1e2c5a9edc8e7e4f16 /drivers/gpu/drm/radeon/r600.c
parentb574f251f787c5b163da5ea345525569e51775bc (diff)
drm/radeon/kms: Fix AGP support for R600/RV770 family (v2)
For AGP to work unmapped access must cover VRAM & AGP as AGP is treated like VRAM by the GPU (ie physical address). This patch properly setup the virtual memory system aperture to cover AGP if AGP is enabled. It seems that there is memory corruption after resume when using AGP (RV770 seems unaffected thought). Version 2 just fix merge issue with updated AGP fallback patch. Signed-off-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/r600.c')
-rw-r--r--drivers/gpu/drm/radeon/r600.c117
1 files changed, 92 insertions, 25 deletions
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index 2cef638fa069..6b43a95a5fb2 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -65,16 +65,11 @@ MODULE_FIRMWARE("radeon/RV710_me.bin");
65 65
66int r600_debugfs_mc_info_init(struct radeon_device *rdev); 66int r600_debugfs_mc_info_init(struct radeon_device *rdev);
67 67
68/* This files gather functions specifics to: 68/* r600,rv610,rv630,rv620,rv635,rv670 */
69 * r600,rv610,rv630,rv620,rv635,rv670
70 *
71 * Some of these functions might be used by newer ASICs.
72 */
73int r600_mc_wait_for_idle(struct radeon_device *rdev); 69int r600_mc_wait_for_idle(struct radeon_device *rdev);
74void r600_gpu_init(struct radeon_device *rdev); 70void r600_gpu_init(struct radeon_device *rdev);
75void r600_fini(struct radeon_device *rdev); 71void r600_fini(struct radeon_device *rdev);
76 72
77
78/* 73/*
79 * R600 PCIE GART 74 * R600 PCIE GART
80 */ 75 */
@@ -168,7 +163,7 @@ int r600_pcie_gart_enable(struct radeon_device *rdev)
168 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); 163 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
169 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); 164 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
170 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12); 165 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
171 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, (rdev->mc.gtt_end - 1) >> 12); 166 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
172 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); 167 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
173 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | 168 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
174 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT); 169 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
@@ -225,6 +220,40 @@ void r600_pcie_gart_fini(struct radeon_device *rdev)
225 radeon_gart_fini(rdev); 220 radeon_gart_fini(rdev);
226} 221}
227 222
223void r600_agp_enable(struct radeon_device *rdev)
224{
225 u32 tmp;
226 int i;
227
228 /* Setup L2 cache */
229 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
230 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
231 EFFECTIVE_L2_QUEUE_SIZE(7));
232 WREG32(VM_L2_CNTL2, 0);
233 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
234 /* Setup TLB control */
235 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
236 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
237 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
238 ENABLE_WAIT_L2_QUERY;
239 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
240 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
241 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
242 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
243 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
244 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
245 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
246 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
247 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
248 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
249 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
250 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
251 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
252 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
253 for (i = 0; i < 7; i++)
254 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
255}
256
228int r600_mc_wait_for_idle(struct radeon_device *rdev) 257int r600_mc_wait_for_idle(struct radeon_device *rdev)
229{ 258{
230 unsigned i; 259 unsigned i;
@@ -263,18 +292,34 @@ static void r600_mc_program(struct radeon_device *rdev)
263 /* Lockout access through VGA aperture (doesn't exist before R600) */ 292 /* Lockout access through VGA aperture (doesn't exist before R600) */
264 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE); 293 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
265 /* Update configuration */ 294 /* Update configuration */
266 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12); 295 if (rdev->flags & RADEON_IS_AGP) {
267 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, (rdev->mc.vram_end - 1) >> 12); 296 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
297 /* VRAM before AGP */
298 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
299 rdev->mc.vram_start >> 12);
300 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
301 rdev->mc.gtt_end >> 12);
302 } else {
303 /* VRAM after AGP */
304 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
305 rdev->mc.gtt_start >> 12);
306 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
307 rdev->mc.vram_end >> 12);
308 }
309 } else {
310 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12);
311 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12);
312 }
268 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0); 313 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
269 tmp = (((rdev->mc.vram_end - 1) >> 24) & 0xFFFF) << 16; 314 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
270 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF); 315 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
271 WREG32(MC_VM_FB_LOCATION, tmp); 316 WREG32(MC_VM_FB_LOCATION, tmp);
272 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8)); 317 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
273 WREG32(HDP_NONSURFACE_INFO, (2 << 7)); 318 WREG32(HDP_NONSURFACE_INFO, (2 << 7));
274 WREG32(HDP_NONSURFACE_SIZE, (rdev->mc.mc_vram_size - 1) | 0x3FF); 319 WREG32(HDP_NONSURFACE_SIZE, rdev->mc.mc_vram_size | 0x3FF);
275 if (rdev->flags & RADEON_IS_AGP) { 320 if (rdev->flags & RADEON_IS_AGP) {
276 WREG32(MC_VM_AGP_TOP, (rdev->mc.gtt_end - 1) >> 16); 321 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22);
277 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16); 322 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22);
278 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22); 323 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
279 } else { 324 } else {
280 WREG32(MC_VM_AGP_BASE, 0); 325 WREG32(MC_VM_AGP_BASE, 0);
@@ -390,9 +435,9 @@ int r600_mc_init(struct radeon_device *rdev)
390 } 435 }
391 } 436 }
392 rdev->mc.vram_start = rdev->mc.vram_location; 437 rdev->mc.vram_start = rdev->mc.vram_location;
393 rdev->mc.vram_end = rdev->mc.vram_location + rdev->mc.mc_vram_size; 438 rdev->mc.vram_end = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1;
394 rdev->mc.gtt_start = rdev->mc.gtt_location; 439 rdev->mc.gtt_start = rdev->mc.gtt_location;
395 rdev->mc.gtt_end = rdev->mc.gtt_location + rdev->mc.gtt_size; 440 rdev->mc.gtt_end = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
396 /* FIXME: we should enforce default clock in case GPU is not in 441 /* FIXME: we should enforce default clock in case GPU is not in
397 * default setup 442 * default setup
398 */ 443 */
@@ -428,9 +473,13 @@ int r600_gpu_soft_reset(struct radeon_device *rdev)
428 u32 srbm_reset = 0; 473 u32 srbm_reset = 0;
429 u32 tmp; 474 u32 tmp;
430 475
431 dev_info(rdev->dev, "GPU softreset (R_008010_GRBM_STATUS=0x%08X " 476 dev_info(rdev->dev, "GPU softreset \n");
432 "R_008014_GRBM_STATUS2=0x%08X)\n", RREG32(R_008010_GRBM_STATUS), 477 dev_info(rdev->dev, " R_008010_GRBM_STATUS=0x%08X\n",
478 RREG32(R_008010_GRBM_STATUS));
479 dev_info(rdev->dev, " R_008014_GRBM_STATUS2=0x%08X\n",
433 RREG32(R_008014_GRBM_STATUS2)); 480 RREG32(R_008014_GRBM_STATUS2));
481 dev_info(rdev->dev, " R_000E50_SRBM_STATUS=0x%08X\n",
482 RREG32(R_000E50_SRBM_STATUS));
434 rv515_mc_stop(rdev, &save); 483 rv515_mc_stop(rdev, &save);
435 if (r600_mc_wait_for_idle(rdev)) { 484 if (r600_mc_wait_for_idle(rdev)) {
436 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); 485 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
@@ -453,7 +502,7 @@ int r600_gpu_soft_reset(struct radeon_device *rdev)
453 S_008020_SOFT_RESET_TA(1) | 502 S_008020_SOFT_RESET_TA(1) |
454 S_008020_SOFT_RESET_VC(1) | 503 S_008020_SOFT_RESET_VC(1) |
455 S_008020_SOFT_RESET_VGT(1); 504 S_008020_SOFT_RESET_VGT(1);
456 dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp); 505 dev_info(rdev->dev, " R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
457 WREG32(R_008020_GRBM_SOFT_RESET, tmp); 506 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
458 (void)RREG32(R_008020_GRBM_SOFT_RESET); 507 (void)RREG32(R_008020_GRBM_SOFT_RESET);
459 udelay(50); 508 udelay(50);
@@ -491,7 +540,14 @@ int r600_gpu_soft_reset(struct radeon_device *rdev)
491 srbm_reset |= S_000E60_SOFT_RESET_RLC(1); 540 srbm_reset |= S_000E60_SOFT_RESET_RLC(1);
492 if (G_000E50_SEM_BUSY(RREG32(R_000E50_SRBM_STATUS))) 541 if (G_000E50_SEM_BUSY(RREG32(R_000E50_SRBM_STATUS)))
493 srbm_reset |= S_000E60_SOFT_RESET_SEM(1); 542 srbm_reset |= S_000E60_SOFT_RESET_SEM(1);
494 dev_info(rdev->dev, "R_000E60_SRBM_SOFT_RESET=0x%08X\n", srbm_reset); 543 if (G_000E50_BIF_BUSY(RREG32(R_000E50_SRBM_STATUS)))
544 srbm_reset |= S_000E60_SOFT_RESET_BIF(1);
545 dev_info(rdev->dev, " R_000E60_SRBM_SOFT_RESET=0x%08X\n", srbm_reset);
546 WREG32(R_000E60_SRBM_SOFT_RESET, srbm_reset);
547 (void)RREG32(R_000E60_SRBM_SOFT_RESET);
548 udelay(50);
549 WREG32(R_000E60_SRBM_SOFT_RESET, 0);
550 (void)RREG32(R_000E60_SRBM_SOFT_RESET);
495 WREG32(R_000E60_SRBM_SOFT_RESET, srbm_reset); 551 WREG32(R_000E60_SRBM_SOFT_RESET, srbm_reset);
496 (void)RREG32(R_000E60_SRBM_SOFT_RESET); 552 (void)RREG32(R_000E60_SRBM_SOFT_RESET);
497 udelay(50); 553 udelay(50);
@@ -499,6 +555,12 @@ int r600_gpu_soft_reset(struct radeon_device *rdev)
499 (void)RREG32(R_000E60_SRBM_SOFT_RESET); 555 (void)RREG32(R_000E60_SRBM_SOFT_RESET);
500 /* Wait a little for things to settle down */ 556 /* Wait a little for things to settle down */
501 udelay(50); 557 udelay(50);
558 dev_info(rdev->dev, " R_008010_GRBM_STATUS=0x%08X\n",
559 RREG32(R_008010_GRBM_STATUS));
560 dev_info(rdev->dev, " R_008014_GRBM_STATUS2=0x%08X\n",
561 RREG32(R_008014_GRBM_STATUS2));
562 dev_info(rdev->dev, " R_000E50_SRBM_STATUS=0x%08X\n",
563 RREG32(R_000E50_SRBM_STATUS));
502 /* After reset we need to reinit the asic as GPU often endup in an 564 /* After reset we need to reinit the asic as GPU often endup in an
503 * incoherent state. 565 * incoherent state.
504 */ 566 */
@@ -1442,9 +1504,13 @@ int r600_startup(struct radeon_device *rdev)
1442 int r; 1504 int r;
1443 1505
1444 r600_mc_program(rdev); 1506 r600_mc_program(rdev);
1445 r = r600_pcie_gart_enable(rdev); 1507 if (rdev->flags & RADEON_IS_AGP) {
1446 if (r) 1508 r600_agp_enable(rdev);
1447 return r; 1509 } else {
1510 r = r600_pcie_gart_enable(rdev);
1511 if (r)
1512 return r;
1513 }
1448 r600_gpu_init(rdev); 1514 r600_gpu_init(rdev);
1449 1515
1450 r = radeon_object_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM, 1516 r = radeon_object_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM,
@@ -1472,9 +1538,10 @@ int r600_resume(struct radeon_device *rdev)
1472{ 1538{
1473 int r; 1539 int r;
1474 1540
1475 if (r600_gpu_reset(rdev)) { 1541 /* Do not reset GPU before posting, on r600 hw unlike on r500 hw,
1476 /* FIXME: what do we want to do here ? */ 1542 * posting will perform necessary task to bring back GPU into good
1477 } 1543 * shape.
1544 */
1478 /* post card */ 1545 /* post card */
1479 atom_asic_init(rdev->mode_info.atom_context); 1546 atom_asic_init(rdev->mode_info.atom_context);
1480 /* Initialize clocks */ 1547 /* Initialize clocks */