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authorAlex Deucher <alexander.deucher@amd.com>2013-09-03 19:00:09 -0400
committerAlex Deucher <alexander.deucher@amd.com>2013-09-11 11:44:29 -0400
commit0a5b7b0bd97a212f5d8d28c5011b04a45dfb006e (patch)
treeac0d7f0e8a81cec0db2a1d4b9e19d4fe1ece0918 /drivers/gpu/drm/radeon/r600.c
parentfe78118c4603ab91b88907eaabe4a1ca03a9f220 (diff)
drm/radeon: add spinlocks for indirect register accesss
This adds spinlocks to protect access to other indirect register apertures. These indirect spaces are used pretty infrequently and we haven't had an reported problems, but better safe than sorry. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/r600.c')
-rw-r--r--drivers/gpu/drm/radeon/r600.c14
1 files changed, 14 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index ea4d3734e6d9..11cd99e3cbb5 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -1045,20 +1045,27 @@ int r600_mc_wait_for_idle(struct radeon_device *rdev)
1045 1045
1046uint32_t rs780_mc_rreg(struct radeon_device *rdev, uint32_t reg) 1046uint32_t rs780_mc_rreg(struct radeon_device *rdev, uint32_t reg)
1047{ 1047{
1048 unsigned long flags;
1048 uint32_t r; 1049 uint32_t r;
1049 1050
1051 spin_lock_irqsave(&rdev->mc_idx_lock, flags);
1050 WREG32(R_0028F8_MC_INDEX, S_0028F8_MC_IND_ADDR(reg)); 1052 WREG32(R_0028F8_MC_INDEX, S_0028F8_MC_IND_ADDR(reg));
1051 r = RREG32(R_0028FC_MC_DATA); 1053 r = RREG32(R_0028FC_MC_DATA);
1052 WREG32(R_0028F8_MC_INDEX, ~C_0028F8_MC_IND_ADDR); 1054 WREG32(R_0028F8_MC_INDEX, ~C_0028F8_MC_IND_ADDR);
1055 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
1053 return r; 1056 return r;
1054} 1057}
1055 1058
1056void rs780_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 1059void rs780_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1057{ 1060{
1061 unsigned long flags;
1062
1063 spin_lock_irqsave(&rdev->mc_idx_lock, flags);
1058 WREG32(R_0028F8_MC_INDEX, S_0028F8_MC_IND_ADDR(reg) | 1064 WREG32(R_0028F8_MC_INDEX, S_0028F8_MC_IND_ADDR(reg) |
1059 S_0028F8_MC_IND_WR_EN(1)); 1065 S_0028F8_MC_IND_WR_EN(1));
1060 WREG32(R_0028FC_MC_DATA, v); 1066 WREG32(R_0028FC_MC_DATA, v);
1061 WREG32(R_0028F8_MC_INDEX, 0x7F); 1067 WREG32(R_0028F8_MC_INDEX, 0x7F);
1068 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
1062} 1069}
1063 1070
1064static void r600_mc_program(struct radeon_device *rdev) 1071static void r600_mc_program(struct radeon_device *rdev)
@@ -2092,20 +2099,27 @@ static void r600_gpu_init(struct radeon_device *rdev)
2092 */ 2099 */
2093u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg) 2100u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg)
2094{ 2101{
2102 unsigned long flags;
2095 u32 r; 2103 u32 r;
2096 2104
2105 spin_lock_irqsave(&rdev->pciep_idx_lock, flags);
2097 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff)); 2106 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
2098 (void)RREG32(PCIE_PORT_INDEX); 2107 (void)RREG32(PCIE_PORT_INDEX);
2099 r = RREG32(PCIE_PORT_DATA); 2108 r = RREG32(PCIE_PORT_DATA);
2109 spin_unlock_irqrestore(&rdev->pciep_idx_lock, flags);
2100 return r; 2110 return r;
2101} 2111}
2102 2112
2103void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v) 2113void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2104{ 2114{
2115 unsigned long flags;
2116
2117 spin_lock_irqsave(&rdev->pciep_idx_lock, flags);
2105 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff)); 2118 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
2106 (void)RREG32(PCIE_PORT_INDEX); 2119 (void)RREG32(PCIE_PORT_INDEX);
2107 WREG32(PCIE_PORT_DATA, (v)); 2120 WREG32(PCIE_PORT_DATA, (v));
2108 (void)RREG32(PCIE_PORT_DATA); 2121 (void)RREG32(PCIE_PORT_DATA);
2122 spin_unlock_irqrestore(&rdev->pciep_idx_lock, flags);
2109} 2123}
2110 2124
2111/* 2125/*