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authorDave Airlie <airlied@redhat.com>2011-10-18 05:54:30 -0400
committerDave Airlie <airlied@redhat.com>2011-10-18 05:54:30 -0400
commit017ed8012e74ca15748863f45d2c078453026a0a (patch)
tree7071171a06de4e93fc890e0afce5c23596a26619 /drivers/gpu/drm/radeon/r600.c
parent80d9b24a658c83602aea66e45e2347c5bb3cbd47 (diff)
parent899e3ee404961a90b828ad527573aaaac39f0ab1 (diff)
Merge tag 'v3.1-rc10' into drm-core-next
There are a number of fixes in mainline required for code in -next, also there was a few conflicts I'd rather resolve myself. Signed-off-by: Dave Airlie <airlied@redhat.com> Conflicts: drivers/gpu/drm/radeon/evergreen.c drivers/gpu/drm/radeon/r600.c drivers/gpu/drm/radeon/radeon_asic.h
Diffstat (limited to 'drivers/gpu/drm/radeon/r600.c')
-rw-r--r--drivers/gpu/drm/radeon/r600.c14
1 files changed, 8 insertions, 6 deletions
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index e87f5662a104..12470b090ddf 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -2212,7 +2212,8 @@ int r600_cp_resume(struct radeon_device *rdev)
2212 /* Initialize the ring buffer's read and write pointers */ 2212 /* Initialize the ring buffer's read and write pointers */
2213 WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA); 2213 WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
2214 WREG32(CP_RB_RPTR_WR, 0); 2214 WREG32(CP_RB_RPTR_WR, 0);
2215 WREG32(CP_RB_WPTR, 0); 2215 rdev->cp.wptr = 0;
2216 WREG32(CP_RB_WPTR, rdev->cp.wptr);
2216 2217
2217 /* set the wb address whether it's enabled or not */ 2218 /* set the wb address whether it's enabled or not */
2218 WREG32(CP_RB_RPTR_ADDR, 2219 WREG32(CP_RB_RPTR_ADDR,
@@ -2234,7 +2235,6 @@ int r600_cp_resume(struct radeon_device *rdev)
2234 WREG32(CP_DEBUG, (1 << 27) | (1 << 28)); 2235 WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
2235 2236
2236 rdev->cp.rptr = RREG32(CP_RB_RPTR); 2237 rdev->cp.rptr = RREG32(CP_RB_RPTR);
2237 rdev->cp.wptr = RREG32(CP_RB_WPTR);
2238 2238
2239 r600_cp_start(rdev); 2239 r600_cp_start(rdev);
2240 rdev->cp.ready = true; 2240 rdev->cp.ready = true;
@@ -2356,21 +2356,23 @@ void r600_fence_ring_emit(struct radeon_device *rdev,
2356} 2356}
2357 2357
2358int r600_copy_blit(struct radeon_device *rdev, 2358int r600_copy_blit(struct radeon_device *rdev,
2359 uint64_t src_offset, uint64_t dst_offset, 2359 uint64_t src_offset,
2360 unsigned num_pages, struct radeon_fence *fence) 2360 uint64_t dst_offset,
2361 unsigned num_gpu_pages,
2362 struct radeon_fence *fence)
2361{ 2363{
2362 int r; 2364 int r;
2363 2365
2364 mutex_lock(&rdev->r600_blit.mutex); 2366 mutex_lock(&rdev->r600_blit.mutex);
2365 rdev->r600_blit.vb_ib = NULL; 2367 rdev->r600_blit.vb_ib = NULL;
2366 r = r600_blit_prepare_copy(rdev, num_pages); 2368 r = r600_blit_prepare_copy(rdev, num_gpu_pages);
2367 if (r) { 2369 if (r) {
2368 if (rdev->r600_blit.vb_ib) 2370 if (rdev->r600_blit.vb_ib)
2369 radeon_ib_free(rdev, &rdev->r600_blit.vb_ib); 2371 radeon_ib_free(rdev, &rdev->r600_blit.vb_ib);
2370 mutex_unlock(&rdev->r600_blit.mutex); 2372 mutex_unlock(&rdev->r600_blit.mutex);
2371 return r; 2373 return r;
2372 } 2374 }
2373 r600_kms_blit_copy(rdev, src_offset, dst_offset, num_pages); 2375 r600_kms_blit_copy(rdev, src_offset, dst_offset, num_gpu_pages);
2374 r600_blit_done_copy(rdev, fence); 2376 r600_blit_done_copy(rdev, fence);
2375 mutex_unlock(&rdev->r600_blit.mutex); 2377 mutex_unlock(&rdev->r600_blit.mutex);
2376 return 0; 2378 return 0;