drm/radeon: UVD bringup v8

Just everything needed to decode videos using UVD.

v6: just all the bugfixes and support for R7xx-SI merged in one patch
v7: UVD_CGC_GATE is a write only register, lockup detection fix
v8: split out VRAM fallback changes, remove support for RV770,
    add support for HEMLOCK, add buffer sizes checks

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

1 files changed, 291 insertions, 0 deletions

diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index 1c5308778948..7ce7b83c76f5 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -2552,6 +2552,185 @@ void r600_dma_fini(struct radeon_device *rdev)
 }
 
 /*
+ * UVD
+ */
+int r600_uvd_rbc_start(struct radeon_device *rdev)
+{
+        struct radeon_ring *ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
+        uint64_t rptr_addr;
+        uint32_t rb_bufsz, tmp;
+        int r;
+
+        rptr_addr = rdev->wb.gpu_addr + R600_WB_UVD_RPTR_OFFSET;
+
+        if (upper_32_bits(rptr_addr) != upper_32_bits(ring->gpu_addr)) {
+                DRM_ERROR("UVD ring and rptr not in the same 4GB segment!\n");
+                return -EINVAL;
+        }
+
+        /* force RBC into idle state */
+        WREG32(UVD_RBC_RB_CNTL, 0x11010101);
+
+        /* Set the write pointer delay */
+        WREG32(UVD_RBC_RB_WPTR_CNTL, 0);
+
+        /* set the wb address */
+        WREG32(UVD_RBC_RB_RPTR_ADDR, rptr_addr >> 2);
+
+        /* programm the 4GB memory segment for rptr and ring buffer */
+        WREG32(UVD_LMI_EXT40_ADDR, upper_32_bits(rptr_addr) |
+                                   (0x7 << 16) | (0x1 << 31));
+
+        /* Initialize the ring buffer's read and write pointers */
+        WREG32(UVD_RBC_RB_RPTR, 0x0);
+
+        ring->wptr = ring->rptr = RREG32(UVD_RBC_RB_RPTR);
+        WREG32(UVD_RBC_RB_WPTR, ring->wptr);
+
+        /* set the ring address */
+        WREG32(UVD_RBC_RB_BASE, ring->gpu_addr);
+
+        /* Set ring buffer size */
+        rb_bufsz = drm_order(ring->ring_size);
+        rb_bufsz = (0x1 << 8) | rb_bufsz;
+        WREG32(UVD_RBC_RB_CNTL, rb_bufsz);
+
+        ring->ready = true;
+        r = radeon_ring_test(rdev, R600_RING_TYPE_UVD_INDEX, ring);
+        if (r) {
+                ring->ready = false;
+                return r;
+        }
+
+        r = radeon_ring_lock(rdev, ring, 10);
+        if (r) {
+                DRM_ERROR("radeon: ring failed to lock UVD ring (%d).\n", r);
+                return r;
+        }
+
+        tmp = PACKET0(UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0);
+        radeon_ring_write(ring, tmp);
+        radeon_ring_write(ring, 0xFFFFF);
+
+        tmp = PACKET0(UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0);
+        radeon_ring_write(ring, tmp);
+        radeon_ring_write(ring, 0xFFFFF);
+
+        tmp = PACKET0(UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0);
+        radeon_ring_write(ring, tmp);
+        radeon_ring_write(ring, 0xFFFFF);
+
+        /* Clear timeout status bits */
+        radeon_ring_write(ring, PACKET0(UVD_SEMA_TIMEOUT_STATUS, 0));
+        radeon_ring_write(ring, 0x8);
+
+        radeon_ring_write(ring, PACKET0(UVD_SEMA_CNTL, 0));
+        radeon_ring_write(ring, 1);
+
+        radeon_ring_unlock_commit(rdev, ring);
+
+        return 0;
+}
+
+void r600_uvd_rbc_stop(struct radeon_device *rdev)
+{
+        struct radeon_ring *ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
+
+        /* force RBC into idle state */
+        WREG32(UVD_RBC_RB_CNTL, 0x11010101);
+        ring->ready = false;
+}
+
+int r600_uvd_init(struct radeon_device *rdev)
+{
+        int i, j, r;
+
+        /* disable clock gating */
+        WREG32(UVD_CGC_GATE, 0);
+
+        /* disable interupt */
+        WREG32_P(UVD_MASTINT_EN, 0, ~(1 << 1));
+
+        /* put LMI, VCPU, RBC etc... into reset */
+        WREG32(UVD_SOFT_RESET, LMI_SOFT_RESET | VCPU_SOFT_RESET |
+               LBSI_SOFT_RESET | RBC_SOFT_RESET | CSM_SOFT_RESET |
+               CXW_SOFT_RESET | TAP_SOFT_RESET | LMI_UMC_SOFT_RESET);
+        mdelay(5);
+
+        /* take UVD block out of reset */
+        WREG32_P(SRBM_SOFT_RESET, 0, ~SOFT_RESET_UVD);
+        mdelay(5);
+
+        /* initialize UVD memory controller */
+        WREG32(UVD_LMI_CTRL, 0x40 | (1 << 8) | (1 << 13) |
+                             (1 << 21) | (1 << 9) | (1 << 20));
+
+        /* disable byte swapping */
+        WREG32(UVD_LMI_SWAP_CNTL, 0);
+        WREG32(UVD_MP_SWAP_CNTL, 0);
+
+        WREG32(UVD_MPC_SET_MUXA0, 0x40c2040);
+        WREG32(UVD_MPC_SET_MUXA1, 0x0);
+        WREG32(UVD_MPC_SET_MUXB0, 0x40c2040);
+        WREG32(UVD_MPC_SET_MUXB1, 0x0);
+        WREG32(UVD_MPC_SET_ALU, 0);
+        WREG32(UVD_MPC_SET_MUX, 0x88);
+
+        /* Stall UMC */
+        WREG32_P(UVD_LMI_CTRL2, 1 << 8, ~(1 << 8));
+        WREG32_P(UVD_RB_ARB_CTRL, 1 << 3, ~(1 << 3));
+
+        /* take all subblocks out of reset, except VCPU */
+        WREG32(UVD_SOFT_RESET, VCPU_SOFT_RESET);
+        mdelay(5);
+
+        /* enable VCPU clock */
+        WREG32(UVD_VCPU_CNTL,  1 << 9);
+
+        /* enable UMC */
+        WREG32_P(UVD_LMI_CTRL2, 0, ~(1 << 8));
+
+        /* boot up the VCPU */
+        WREG32(UVD_SOFT_RESET, 0);
+        mdelay(10);
+
+        WREG32_P(UVD_RB_ARB_CTRL, 0, ~(1 << 3));
+
+        for (i = 0; i < 10; ++i) {
+                uint32_t status;
+                for (j = 0; j < 100; ++j) {
+                        status = RREG32(UVD_STATUS);
+                        if (status & 2)
+                                break;
+                        mdelay(10);
+                }
+                r = 0;
+                if (status & 2)
+                        break;
+
+                DRM_ERROR("UVD not responding, trying to reset the VCPU!!!\n");
+                WREG32_P(UVD_SOFT_RESET, VCPU_SOFT_RESET, ~VCPU_SOFT_RESET);
+                mdelay(10);
+                WREG32_P(UVD_SOFT_RESET, 0, ~VCPU_SOFT_RESET);
+                mdelay(10);
+                r = -1;
+        }
+        if (r) {
+                DRM_ERROR("UVD not responding, giving up!!!\n");
+                return r;
+        }
+        /* enable interupt */
+        WREG32_P(UVD_MASTINT_EN, 3<<1, ~(3 << 1));
+
+        r = r600_uvd_rbc_start(rdev);
+        if (r)
+                return r;
+
+        DRM_INFO("UVD initialized successfully.\n");
+        return 0;
+}
+
+/*
  * GPU scratch registers helpers function.
  */
 void r600_scratch_init(struct radeon_device *rdev)
@@ -2660,6 +2839,40 @@ int r600_dma_ring_test(struct radeon_device *rdev,
         return r;
 }
 
+int r600_uvd_ring_test(struct radeon_device *rdev, struct radeon_ring *ring)
+{
+        uint32_t tmp = 0;
+        unsigned i;
+        int r;
+
+        WREG32(UVD_CONTEXT_ID, 0xCAFEDEAD);
+        r = radeon_ring_lock(rdev, ring, 3);
+        if (r) {
+                DRM_ERROR("radeon: cp failed to lock ring %d (%d).\n",
+                          ring->idx, r);
+                return r;
+        }
+        radeon_ring_write(ring, PACKET0(UVD_CONTEXT_ID, 0));
+        radeon_ring_write(ring, 0xDEADBEEF);
+        radeon_ring_unlock_commit(rdev, ring);
+        for (i = 0; i < rdev->usec_timeout; i++) {
+                tmp = RREG32(UVD_CONTEXT_ID);
+                if (tmp == 0xDEADBEEF)
+                        break;
+                DRM_UDELAY(1);
+        }
+
+        if (i < rdev->usec_timeout) {
+                DRM_INFO("ring test on %d succeeded in %d usecs\n",
+                         ring->idx, i);
+        } else {
+                DRM_ERROR("radeon: ring %d test failed (0x%08X)\n",
+                          ring->idx, tmp);
+                r = -EINVAL;
+        }
+        return r;
+}
+
 /*
  * CP fences/semaphores
  */
@@ -2711,6 +2924,30 @@ void r600_fence_ring_emit(struct radeon_device *rdev,
         }
 }
 
+void r600_uvd_fence_emit(struct radeon_device *rdev,
+                         struct radeon_fence *fence)
+{
+        struct radeon_ring *ring = &rdev->ring[fence->ring];
+        uint32_t addr = rdev->fence_drv[fence->ring].gpu_addr;
+
+        radeon_ring_write(ring, PACKET0(UVD_CONTEXT_ID, 0));
+        radeon_ring_write(ring, fence->seq);
+        radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA0, 0));
+        radeon_ring_write(ring, addr & 0xffffffff);
+        radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA1, 0));
+        radeon_ring_write(ring, upper_32_bits(addr) & 0xff);
+        radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_CMD, 0));
+        radeon_ring_write(ring, 0);
+
+        radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA0, 0));
+        radeon_ring_write(ring, 0);
+        radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA1, 0));
+        radeon_ring_write(ring, 0);
+        radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_CMD, 0));
+        radeon_ring_write(ring, 2);
+        return;
+}
+
 void r600_semaphore_ring_emit(struct radeon_device *rdev,
                               struct radeon_ring *ring,
                               struct radeon_semaphore *semaphore,
@@ -2780,6 +3017,23 @@ void r600_dma_semaphore_ring_emit(struct radeon_device *rdev,
         radeon_ring_write(ring, upper_32_bits(addr) & 0xff);
 }
 
+void r600_uvd_semaphore_emit(struct radeon_device *rdev,
+                             struct radeon_ring *ring,
+                             struct radeon_semaphore *semaphore,
+                             bool emit_wait)
+{
+        uint64_t addr = semaphore->gpu_addr;
+
+        radeon_ring_write(ring, PACKET0(UVD_SEMA_ADDR_LOW, 0));
+        radeon_ring_write(ring, (addr >> 3) & 0x000FFFFF);
+
+        radeon_ring_write(ring, PACKET0(UVD_SEMA_ADDR_HIGH, 0));
+        radeon_ring_write(ring, (addr >> 23) & 0x000FFFFF);
+
+        radeon_ring_write(ring, PACKET0(UVD_SEMA_CMD, 0));
+        radeon_ring_write(ring, emit_wait ? 1 : 0);
+}
+
 int r600_copy_blit(struct radeon_device *rdev,
                    uint64_t src_offset,
                    uint64_t dst_offset,
@@ -3183,6 +3437,16 @@ void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
         radeon_ring_write(ring, ib->length_dw);
 }
 
+void r600_uvd_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
+{
+        struct radeon_ring *ring = &rdev->ring[ib->ring];
+
+        radeon_ring_write(ring, PACKET0(UVD_RBC_IB_BASE, 0));
+        radeon_ring_write(ring, ib->gpu_addr);
+        radeon_ring_write(ring, PACKET0(UVD_RBC_IB_SIZE, 0));
+        radeon_ring_write(ring, ib->length_dw);
+}
+
 int r600_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
 {
         struct radeon_ib ib;
@@ -3300,6 +3564,33 @@ int r600_dma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
         return r;
 }
 
+int r600_uvd_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
+{
+        struct radeon_fence *fence;
+        int r;
+
+        r = radeon_uvd_get_create_msg(rdev, ring->idx, 1, NULL);
+        if (r) {
+                DRM_ERROR("radeon: failed to get create msg (%d).\n", r);
+                return r;
+        }
+
+        r = radeon_uvd_get_destroy_msg(rdev, ring->idx, 1, &fence);
+        if (r) {
+                DRM_ERROR("radeon: failed to get destroy ib (%d).\n", r);
+                return r;
+        }
+
+        r = radeon_fence_wait(fence, false);
+        if (r) {
+                DRM_ERROR("radeon: fence wait failed (%d).\n", r);
+                return r;
+        }
+        DRM_INFO("ib test on ring %d succeeded\n",  ring->idx);
+        radeon_fence_unref(&fence);
+        return r;
+}
+
 /**
  * r600_dma_ring_ib_execute - Schedule an IB on the DMA engine
  *