drm/radeon: rename struct radeon_cp to radeon_ring

That naming seems to make more sense, since we not
only want to run PM4 rings with it.

Signed-off-by: Christian König <deathsimple@vodafone.de>
Reviewed-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

1 files changed, 94 insertions, 94 deletions

diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index aaf8cd42943e..d26e7c9f047c 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -1344,7 +1344,7 @@ int r600_gpu_soft_reset(struct radeon_device *rdev)
         return 0;
 }
 
-bool r600_gpu_is_lockup(struct radeon_device *rdev, struct radeon_cp *cp)
+bool r600_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
 {
         u32 srbm_status;
         u32 grbm_status;
@@ -1361,19 +1361,19 @@ bool r600_gpu_is_lockup(struct radeon_device *rdev, struct radeon_cp *cp)
         grbm_status = RREG32(R_008010_GRBM_STATUS);
         grbm_status2 = RREG32(R_008014_GRBM_STATUS2);
         if (!G_008010_GUI_ACTIVE(grbm_status)) {
-                r100_gpu_lockup_update(lockup, cp);
+                r100_gpu_lockup_update(lockup, ring);
                 return false;
         }
         /* force CP activities */
-        r = radeon_ring_lock(rdev, cp, 2);
+        r = radeon_ring_lock(rdev, ring, 2);
         if (!r) {
                 /* PACKET2 NOP */
-                radeon_ring_write(cp, 0x80000000);
-                radeon_ring_write(cp, 0x80000000);
-                radeon_ring_unlock_commit(rdev, cp);
+                radeon_ring_write(ring, 0x80000000);
+                radeon_ring_write(ring, 0x80000000);
+                radeon_ring_unlock_commit(rdev, ring);
         }
-        cp->rptr = RREG32(cp->rptr_reg);
-        return r100_gpu_cp_is_lockup(rdev, lockup, cp);
+        ring->rptr = RREG32(ring->rptr_reg);
+        return r100_gpu_cp_is_lockup(rdev, lockup, ring);
 }
 
 int r600_asic_reset(struct radeon_device *rdev)
@@ -2144,28 +2144,28 @@ static int r600_cp_load_microcode(struct radeon_device *rdev)
 
 int r600_cp_start(struct radeon_device *rdev)
 {
-        struct radeon_cp *cp = &rdev->cp[RADEON_RING_TYPE_GFX_INDEX];
+        struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
         int r;
         uint32_t cp_me;
 
-        r = radeon_ring_lock(rdev, cp, 7);
+        r = radeon_ring_lock(rdev, ring, 7);
         if (r) {
                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
                 return r;
         }
-        radeon_ring_write(cp, PACKET3(PACKET3_ME_INITIALIZE, 5));
-        radeon_ring_write(cp, 0x1);
+        radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
+        radeon_ring_write(ring, 0x1);
         if (rdev->family >= CHIP_RV770) {
-                radeon_ring_write(cp, 0x0);
-                radeon_ring_write(cp, rdev->config.rv770.max_hw_contexts - 1);
+                radeon_ring_write(ring, 0x0);
+                radeon_ring_write(ring, rdev->config.rv770.max_hw_contexts - 1);
         } else {
-                radeon_ring_write(cp, 0x3);
-                radeon_ring_write(cp, rdev->config.r600.max_hw_contexts - 1);
+                radeon_ring_write(ring, 0x3);
+                radeon_ring_write(ring, rdev->config.r600.max_hw_contexts - 1);
         }
-        radeon_ring_write(cp, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
-        radeon_ring_write(cp, 0);
-        radeon_ring_write(cp, 0);
-        radeon_ring_unlock_commit(rdev, cp);
+        radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
+        radeon_ring_write(ring, 0);
+        radeon_ring_write(ring, 0);
+        radeon_ring_unlock_commit(rdev, ring);
 
         cp_me = 0xff;
         WREG32(R_0086D8_CP_ME_CNTL, cp_me);
@@ -2174,7 +2174,7 @@ int r600_cp_start(struct radeon_device *rdev)
 
 int r600_cp_resume(struct radeon_device *rdev)
 {
-        struct radeon_cp *cp = &rdev->cp[RADEON_RING_TYPE_GFX_INDEX];
+        struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
         u32 tmp;
         u32 rb_bufsz;
         int r;
@@ -2186,7 +2186,7 @@ int r600_cp_resume(struct radeon_device *rdev)
         WREG32(GRBM_SOFT_RESET, 0);
 
         /* Set ring buffer size */
-        rb_bufsz = drm_order(cp->ring_size / 8);
+        rb_bufsz = drm_order(ring->ring_size / 8);
         tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
 #ifdef __BIG_ENDIAN
         tmp |= BUF_SWAP_32BIT;
@@ -2200,8 +2200,8 @@ int r600_cp_resume(struct radeon_device *rdev)
         /* Initialize the ring buffer's read and write pointers */
         WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
         WREG32(CP_RB_RPTR_WR, 0);
-        cp->wptr = 0;
-        WREG32(CP_RB_WPTR, cp->wptr);
+        ring->wptr = 0;
+        WREG32(CP_RB_WPTR, ring->wptr);
 
         /* set the wb address whether it's enabled or not */
         WREG32(CP_RB_RPTR_ADDR,
@@ -2219,36 +2219,36 @@ int r600_cp_resume(struct radeon_device *rdev)
         mdelay(1);
         WREG32(CP_RB_CNTL, tmp);
 
-        WREG32(CP_RB_BASE, cp->gpu_addr >> 8);
+        WREG32(CP_RB_BASE, ring->gpu_addr >> 8);
         WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
 
-        cp->rptr = RREG32(CP_RB_RPTR);
+        ring->rptr = RREG32(CP_RB_RPTR);
 
         r600_cp_start(rdev);
-        cp->ready = true;
-        r = radeon_ring_test(rdev, cp);
+        ring->ready = true;
+        r = radeon_ring_test(rdev, ring);
         if (r) {
-                cp->ready = false;
+                ring->ready = false;
                 return r;
         }
         return 0;
 }
 
-void r600_ring_init(struct radeon_device *rdev, struct radeon_cp *cp, unsigned ring_size)
+void r600_ring_init(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ring_size)
 {
         u32 rb_bufsz;
 
         /* Align ring size */
         rb_bufsz = drm_order(ring_size / 8);
         ring_size = (1 << (rb_bufsz + 1)) * 4;
-        cp->ring_size = ring_size;
-        cp->align_mask = 16 - 1;
+        ring->ring_size = ring_size;
+        ring->align_mask = 16 - 1;
 }
 
 void r600_cp_fini(struct radeon_device *rdev)
 {
         r600_cp_stop(rdev);
-        radeon_ring_fini(rdev, &rdev->cp[RADEON_RING_TYPE_GFX_INDEX]);
+        radeon_ring_fini(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
 }
 
 
@@ -2267,11 +2267,11 @@ void r600_scratch_init(struct radeon_device *rdev)
         }
 }
 
-int r600_ring_test(struct radeon_device *rdev, struct radeon_cp *cp)
+int r600_ring_test(struct radeon_device *rdev, struct radeon_ring *ring)
 {
         uint32_t scratch;
         uint32_t tmp = 0;
-        unsigned i, ridx = radeon_ring_index(rdev, cp);
+        unsigned i, ridx = radeon_ring_index(rdev, ring);
         int r;
 
         r = radeon_scratch_get(rdev, &scratch);
@@ -2280,16 +2280,16 @@ int r600_ring_test(struct radeon_device *rdev, struct radeon_cp *cp)
                 return r;
         }
         WREG32(scratch, 0xCAFEDEAD);
-        r = radeon_ring_lock(rdev, cp, 3);
+        r = radeon_ring_lock(rdev, ring, 3);
         if (r) {
                 DRM_ERROR("radeon: cp failed to lock ring %d (%d).\n", ridx, r);
                 radeon_scratch_free(rdev, scratch);
                 return r;
         }
-        radeon_ring_write(cp, PACKET3(PACKET3_SET_CONFIG_REG, 1));
-        radeon_ring_write(cp, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
-        radeon_ring_write(cp, 0xDEADBEEF);
-        radeon_ring_unlock_commit(rdev, cp);
+        radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
+        radeon_ring_write(ring, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
+        radeon_ring_write(ring, 0xDEADBEEF);
+        radeon_ring_unlock_commit(rdev, ring);
         for (i = 0; i < rdev->usec_timeout; i++) {
                 tmp = RREG32(scratch);
                 if (tmp == 0xDEADBEEF)
@@ -2310,62 +2310,62 @@ int r600_ring_test(struct radeon_device *rdev, struct radeon_cp *cp)
 void r600_fence_ring_emit(struct radeon_device *rdev,
                           struct radeon_fence *fence)
 {
-        struct radeon_cp *cp = &rdev->cp[fence->ring];
+        struct radeon_ring *ring = &rdev->ring[fence->ring];
 
         if (rdev->wb.use_event) {
                 u64 addr = rdev->wb.gpu_addr + R600_WB_EVENT_OFFSET +
                         (u64)(rdev->fence_drv[fence->ring].scratch_reg - rdev->scratch.reg_base);
                 /* flush read cache over gart */
-                radeon_ring_write(cp, PACKET3(PACKET3_SURFACE_SYNC, 3));
-                radeon_ring_write(cp, PACKET3_TC_ACTION_ENA |
-                                      PACKET3_VC_ACTION_ENA |
-                                      PACKET3_SH_ACTION_ENA);
-                radeon_ring_write(cp, 0xFFFFFFFF);
-                radeon_ring_write(cp, 0);
-                radeon_ring_write(cp, 10); /* poll interval */
+                radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
+                radeon_ring_write(ring, PACKET3_TC_ACTION_ENA |
+                                        PACKET3_VC_ACTION_ENA |
+                                        PACKET3_SH_ACTION_ENA);
+                radeon_ring_write(ring, 0xFFFFFFFF);
+                radeon_ring_write(ring, 0);
+                radeon_ring_write(ring, 10); /* poll interval */
                 /* EVENT_WRITE_EOP - flush caches, send int */
-                radeon_ring_write(cp, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
-                radeon_ring_write(cp, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5));
-                radeon_ring_write(cp, addr & 0xffffffff);
-                radeon_ring_write(cp, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2));
-                radeon_ring_write(cp, fence->seq);
-                radeon_ring_write(cp, 0);
+                radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
+                radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5));
+                radeon_ring_write(ring, addr & 0xffffffff);
+                radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2));
+                radeon_ring_write(ring, fence->seq);
+                radeon_ring_write(ring, 0);
         } else {
                 /* flush read cache over gart */
-                radeon_ring_write(cp, PACKET3(PACKET3_SURFACE_SYNC, 3));
-                radeon_ring_write(cp, PACKET3_TC_ACTION_ENA |
-                                      PACKET3_VC_ACTION_ENA |
-                                      PACKET3_SH_ACTION_ENA);
-                radeon_ring_write(cp, 0xFFFFFFFF);
-                radeon_ring_write(cp, 0);
-                radeon_ring_write(cp, 10); /* poll interval */
-                radeon_ring_write(cp, PACKET3(PACKET3_EVENT_WRITE, 0));
-                radeon_ring_write(cp, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0));
+                radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
+                radeon_ring_write(ring, PACKET3_TC_ACTION_ENA |
+                                        PACKET3_VC_ACTION_ENA |
+                                        PACKET3_SH_ACTION_ENA);
+                radeon_ring_write(ring, 0xFFFFFFFF);
+                radeon_ring_write(ring, 0);
+                radeon_ring_write(ring, 10); /* poll interval */
+                radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));
+                radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0));
                 /* wait for 3D idle clean */
-                radeon_ring_write(cp, PACKET3(PACKET3_SET_CONFIG_REG, 1));
-                radeon_ring_write(cp, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
-                radeon_ring_write(cp, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit);
+                radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
+                radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
+                radeon_ring_write(ring, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit);
                 /* Emit fence sequence & fire IRQ */
-                radeon_ring_write(cp, PACKET3(PACKET3_SET_CONFIG_REG, 1));
-                radeon_ring_write(cp, ((rdev->fence_drv[fence->ring].scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
-                radeon_ring_write(cp, fence->seq);
+                radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
+                radeon_ring_write(ring, ((rdev->fence_drv[fence->ring].scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
+                radeon_ring_write(ring, fence->seq);
                 /* CP_INTERRUPT packet 3 no longer exists, use packet 0 */
-                radeon_ring_write(cp, PACKET0(CP_INT_STATUS, 0));
-                radeon_ring_write(cp, RB_INT_STAT);
+                radeon_ring_write(ring, PACKET0(CP_INT_STATUS, 0));
+                radeon_ring_write(ring, RB_INT_STAT);
         }
 }
 
 void r600_semaphore_ring_emit(struct radeon_device *rdev,
-                              struct radeon_cp *cp,
+                              struct radeon_ring *ring,
                               struct radeon_semaphore *semaphore,
                               bool emit_wait)
 {
         uint64_t addr = semaphore->gpu_addr;
         unsigned sel = emit_wait ? PACKET3_SEM_SEL_WAIT : PACKET3_SEM_SEL_SIGNAL;
 
-        radeon_ring_write(cp, PACKET3(PACKET3_MEM_SEMAPHORE, 1));
-        radeon_ring_write(cp, addr & 0xffffffff);
-        radeon_ring_write(cp, (upper_32_bits(addr) & 0xff) | sel);
+        radeon_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1));
+        radeon_ring_write(ring, addr & 0xffffffff);
+        radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | sel);
 }
 
 int r600_copy_blit(struct radeon_device *rdev,
@@ -2420,7 +2420,7 @@ void r600_clear_surface_reg(struct radeon_device *rdev, int reg)
 
 int r600_startup(struct radeon_device *rdev)
 {
-        struct radeon_cp *cp = &rdev->cp[RADEON_RING_TYPE_GFX_INDEX];
+        struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
         int r;
 
         /* enable pcie gen2 link */
@@ -2468,7 +2468,7 @@ int r600_startup(struct radeon_device *rdev)
         }
         r600_irq_set(rdev);
 
-        r = radeon_ring_init(rdev, cp, cp->ring_size, RADEON_WB_CP_RPTR_OFFSET,
+        r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
                              R600_CP_RB_RPTR, R600_CP_RB_WPTR);
 
         if (r)
@@ -2534,7 +2534,7 @@ int r600_suspend(struct radeon_device *rdev)
         r600_audio_fini(rdev);
         /* FIXME: we should wait for ring to be empty */
         r600_cp_stop(rdev);
-        rdev->cp[RADEON_RING_TYPE_GFX_INDEX].ready = false;
+        rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
         r600_irq_suspend(rdev);
         radeon_wb_disable(rdev);
         r600_pcie_gart_disable(rdev);
@@ -2609,8 +2609,8 @@ int r600_init(struct radeon_device *rdev)
         if (r)
                 return r;
 
-        rdev->cp[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL;
-        r600_ring_init(rdev, &rdev->cp[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024);
+        rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL;
+        r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024);
 
         rdev->ih.ring_obj = NULL;
         r600_ih_ring_init(rdev, 64 * 1024);
@@ -2677,17 +2677,17 @@ void r600_fini(struct radeon_device *rdev)
  */
 void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
 {
-        struct radeon_cp *cp = &rdev->cp[ib->fence->ring];
+        struct radeon_ring *ring = &rdev->ring[ib->fence->ring];
 
         /* FIXME: implement */
-        radeon_ring_write(cp, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
-        radeon_ring_write(cp,
+        radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
+        radeon_ring_write(ring,
 #ifdef __BIG_ENDIAN
                           (2 << 0) |
 #endif
                           (ib->gpu_addr & 0xFFFFFFFC));
-        radeon_ring_write(cp, upper_32_bits(ib->gpu_addr) & 0xFF);
-        radeon_ring_write(cp, ib->length_dw);
+        radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF);
+        radeon_ring_write(ring, ib->length_dw);
 }
 
 int r600_ib_test(struct radeon_device *rdev, int ring)
@@ -3518,22 +3518,22 @@ static int r600_debugfs_cp_ring_info(struct seq_file *m, void *data)
         struct drm_info_node *node = (struct drm_info_node *) m->private;
         struct drm_device *dev = node->minor->dev;
         struct radeon_device *rdev = dev->dev_private;
-        struct radeon_cp *cp = &rdev->cp[RADEON_RING_TYPE_GFX_INDEX];
+        struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
         unsigned count, i, j;
 
-        radeon_ring_free_size(rdev, cp);
-        count = (cp->ring_size / 4) - cp->ring_free_dw;
+        radeon_ring_free_size(rdev, ring);
+        count = (ring->ring_size / 4) - ring->ring_free_dw;
         seq_printf(m, "CP_STAT 0x%08x\n", RREG32(CP_STAT));
         seq_printf(m, "CP_RB_WPTR 0x%08x\n", RREG32(CP_RB_WPTR));
         seq_printf(m, "CP_RB_RPTR 0x%08x\n", RREG32(CP_RB_RPTR));
-        seq_printf(m, "driver's copy of the CP_RB_WPTR 0x%08x\n", cp->wptr);
-        seq_printf(m, "driver's copy of the CP_RB_RPTR 0x%08x\n", cp->rptr);
-        seq_printf(m, "%u free dwords in ring\n", cp->ring_free_dw);
+        seq_printf(m, "driver's copy of the CP_RB_WPTR 0x%08x\n", ring->wptr);
+        seq_printf(m, "driver's copy of the CP_RB_RPTR 0x%08x\n", ring->rptr);
+        seq_printf(m, "%u free dwords in ring\n", ring->ring_free_dw);
         seq_printf(m, "%u dwords in ring\n", count);
-        i = cp->rptr;
+        i = ring->rptr;
         for (j = 0; j <= count; j++) {
-                seq_printf(m, "r[%04d]=0x%08x\n", i, cp->ring[i]);
-                i = (i + 1) & cp->ptr_mask;
+                seq_printf(m, "r[%04d]=0x%08x\n", i, ring->ring[i]);
+                i = (i + 1) & ring->ptr_mask;
         }
         return 0;
 }