diff options
author | Cédric Cano <ccano@interfaceconcept.com> | 2011-02-11 19:45:38 -0500 |
---|---|---|
committer | Dave Airlie <airlied@redhat.com> | 2011-02-13 18:23:38 -0500 |
commit | 4eace7fdfa1f8ac2f0a833e12bd07eeb453ec9ef (patch) | |
tree | e215856a4eebb3186085e386fa893fdc82c2138e /drivers/gpu/drm/radeon/r600.c | |
parent | 4589433c57bd34b7e49068549e07a43c8d41e39d (diff) |
drm/radeon/kms: 6xx/7xx big endian fixes
agd5f: minor cleanups
Signed-off-by: Cédric Cano <ccano@interfaceconcept.com>
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/r600.c')
-rw-r--r-- | drivers/gpu/drm/radeon/r600.c | 22 |
1 files changed, 17 insertions, 5 deletions
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c index 650672a0f5ad..de88624d5f87 100644 --- a/drivers/gpu/drm/radeon/r600.c +++ b/drivers/gpu/drm/radeon/r600.c | |||
@@ -2105,7 +2105,11 @@ static int r600_cp_load_microcode(struct radeon_device *rdev) | |||
2105 | 2105 | ||
2106 | r600_cp_stop(rdev); | 2106 | r600_cp_stop(rdev); |
2107 | 2107 | ||
2108 | WREG32(CP_RB_CNTL, RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3)); | 2108 | WREG32(CP_RB_CNTL, |
2109 | #ifdef __BIG_ENDIAN | ||
2110 | BUF_SWAP_32BIT | | ||
2111 | #endif | ||
2112 | RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3)); | ||
2109 | 2113 | ||
2110 | /* Reset cp */ | 2114 | /* Reset cp */ |
2111 | WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP); | 2115 | WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP); |
@@ -2192,7 +2196,11 @@ int r600_cp_resume(struct radeon_device *rdev) | |||
2192 | WREG32(CP_RB_WPTR, 0); | 2196 | WREG32(CP_RB_WPTR, 0); |
2193 | 2197 | ||
2194 | /* set the wb address whether it's enabled or not */ | 2198 | /* set the wb address whether it's enabled or not */ |
2195 | WREG32(CP_RB_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC); | 2199 | WREG32(CP_RB_RPTR_ADDR, |
2200 | #ifdef __BIG_ENDIAN | ||
2201 | RB_RPTR_SWAP(2) | | ||
2202 | #endif | ||
2203 | ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC)); | ||
2196 | WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF); | 2204 | WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF); |
2197 | WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF); | 2205 | WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF); |
2198 | 2206 | ||
@@ -2628,7 +2636,11 @@ void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) | |||
2628 | { | 2636 | { |
2629 | /* FIXME: implement */ | 2637 | /* FIXME: implement */ |
2630 | radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); | 2638 | radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); |
2631 | radeon_ring_write(rdev, ib->gpu_addr & 0xFFFFFFFC); | 2639 | radeon_ring_write(rdev, |
2640 | #ifdef __BIG_ENDIAN | ||
2641 | (2 << 0) | | ||
2642 | #endif | ||
2643 | (ib->gpu_addr & 0xFFFFFFFC)); | ||
2632 | radeon_ring_write(rdev, upper_32_bits(ib->gpu_addr) & 0xFF); | 2644 | radeon_ring_write(rdev, upper_32_bits(ib->gpu_addr) & 0xFF); |
2633 | radeon_ring_write(rdev, ib->length_dw); | 2645 | radeon_ring_write(rdev, ib->length_dw); |
2634 | } | 2646 | } |
@@ -3297,8 +3309,8 @@ restart_ih: | |||
3297 | while (rptr != wptr) { | 3309 | while (rptr != wptr) { |
3298 | /* wptr/rptr are in bytes! */ | 3310 | /* wptr/rptr are in bytes! */ |
3299 | ring_index = rptr / 4; | 3311 | ring_index = rptr / 4; |
3300 | src_id = rdev->ih.ring[ring_index] & 0xff; | 3312 | src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff; |
3301 | src_data = rdev->ih.ring[ring_index + 1] & 0xfffffff; | 3313 | src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff; |
3302 | 3314 | ||
3303 | switch (src_id) { | 3315 | switch (src_id) { |
3304 | case 1: /* D1 vblank/vline */ | 3316 | case 1: /* D1 vblank/vline */ |