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authorJerome Glisse <jglisse@redhat.com>2010-02-17 16:54:29 -0500
committerDave Airlie <airlied@redhat.com>2010-02-17 23:49:35 -0500
commitd594e46ace22afa1621254f6f669e65430048153 (patch)
treebefd5b54ce1b8284acc4ee450d085a7d2c7b01fd /drivers/gpu/drm/radeon/r520.c
parent44ca7478d46aaad488d916f7262253e000ee60f9 (diff)
drm/radeon/kms: simplify memory controller setup V2
Get rid of _location and use _start/_end also simplify the computation of vram_start|end & gtt_start|end. For R1XX-R2XX we place VRAM at the same address of PCI aperture, those GPU shouldn't have much memory and seems to behave better when setup that way. For R3XX and newer we place VRAM at 0. For R6XX-R7XX AGP we place VRAM before or after AGP aperture this might limit to limit the VRAM size but it's very unlikely. For IGP we don't change the VRAM placement. Tested on (compiz,quake3,suspend/resume): PCI/PCIE:RV280,R420,RV515,RV570,RV610,RV710 AGP:RV100,RV280,R420,RV350,RV620(RPB*),RV730 IGP:RS480(RPB*),RS690,RS780(RPB*),RS880 RPB: resume previously broken V2 correct commit message to reflect more accurately the bug and move VRAM placement to 0 for most of the GPU to avoid limiting VRAM. Signed-off-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/r520.c')
-rw-r--r--drivers/gpu/drm/radeon/r520.c21
1 files changed, 13 insertions, 8 deletions
diff --git a/drivers/gpu/drm/radeon/r520.c b/drivers/gpu/drm/radeon/r520.c
index ddf5731eba0d..2b8a5dd13516 100644
--- a/drivers/gpu/drm/radeon/r520.c
+++ b/drivers/gpu/drm/radeon/r520.c
@@ -119,13 +119,15 @@ static void r520_vram_get_type(struct radeon_device *rdev)
119 rdev->mc.vram_width *= 2; 119 rdev->mc.vram_width *= 2;
120} 120}
121 121
122void r520_vram_info(struct radeon_device *rdev) 122void r520_mc_init(struct radeon_device *rdev)
123{ 123{
124 fixed20_12 a; 124 fixed20_12 a;
125 125
126 r520_vram_get_type(rdev); 126 r520_vram_get_type(rdev);
127
128 r100_vram_init_sizes(rdev); 127 r100_vram_init_sizes(rdev);
128 radeon_vram_location(rdev, &rdev->mc, 0);
129 if (!(rdev->flags & RADEON_IS_AGP))
130 radeon_gtt_location(rdev, &rdev->mc);
129 /* FIXME: we should enforce default clock in case GPU is not in 131 /* FIXME: we should enforce default clock in case GPU is not in
130 * default setup 132 * default setup
131 */ 133 */
@@ -267,12 +269,15 @@ int r520_init(struct radeon_device *rdev)
267 radeon_get_clock_info(rdev->ddev); 269 radeon_get_clock_info(rdev->ddev);
268 /* Initialize power management */ 270 /* Initialize power management */
269 radeon_pm_init(rdev); 271 radeon_pm_init(rdev);
270 /* Get vram informations */ 272 /* initialize AGP */
271 r520_vram_info(rdev); 273 if (rdev->flags & RADEON_IS_AGP) {
272 /* Initialize memory controller (also test AGP) */ 274 r = radeon_agp_init(rdev);
273 r = r420_mc_init(rdev); 275 if (r) {
274 if (r) 276 radeon_agp_disable(rdev);
275 return r; 277 }
278 }
279 /* initialize memory controller */
280 r520_mc_init(rdev);
276 rv515_debugfs(rdev); 281 rv515_debugfs(rdev);
277 /* Fence driver */ 282 /* Fence driver */
278 r = radeon_fence_driver_init(rdev); 283 r = radeon_fence_driver_init(rdev);