drm/radeon/kms: Convert RS400/RS480 to new init path & fix legacy VGA (V3)

Also cleanup register specific to RS400/RS480. This patch also fix
legacy VGA register used to disable VGA access we were programming
wrong register. Now we should properly disable VGA on r100 up to
rs400 asics. Note that RS400/RS480 resume is broken, it hangs the
computer while reprogramming dynamic clock, doesn't work either
without that patch. We need to spend more time investigating this
issue. Version 2 of the patch remove dead code that was left
commented out in the previous version. Version 3 correct the
placement on IGP of the VRAM inside GPU address space to match the
stollen RAM placement of IGP.

Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

1 files changed, 5 insertions, 0 deletions

diff --git a/drivers/gpu/drm/radeon/r420.c b/drivers/gpu/drm/radeon/r420.c
index 49a2fdc57d27..c5d3ba47f5df 100644
--- a/drivers/gpu/drm/radeon/r420.c
+++ b/drivers/gpu/drm/radeon/r420.c
@@ -155,6 +155,9 @@ static void r420_debugfs(struct radeon_device *rdev)
 static void r420_clock_resume(struct radeon_device *rdev)
 {
         u32 sclk_cntl;
+
+        if (radeon_dynclks != -1 && radeon_dynclks)
+                radeon_atom_set_clock_gating(rdev, 1);
         sclk_cntl = RREG32_PLL(R_00000D_SCLK_CNTL);
         sclk_cntl |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
         if (rdev->family == CHIP_R420)
@@ -167,6 +170,8 @@ static int r420_startup(struct radeon_device *rdev)
         int r;
 
         r300_mc_program(rdev);
+        /* Resume clock */
+        r420_clock_resume(rdev);
         /* Initialize GART (initialize after TTM so we can allocate
          * memory through TTM but finalize after TTM) */
         if (rdev->flags & RADEON_IS_PCIE) {