drm/radeon/kms: move around new init path code to avoid posting at init

We really don't want to post the card at init, it takes a relatively
long time and isn't required, so split the resume path into
a startup path called by both init/resume and separate resume
entry point to do posting.

Signed-off-by: Dave Airlie <airlied@redhat.com>

1 files changed, 29 insertions, 23 deletions

diff --git a/drivers/gpu/drm/radeon/r420.c b/drivers/gpu/drm/radeon/r420.c
index 2142a4781970..9b38956e91c7 100644
--- a/drivers/gpu/drm/radeon/r420.c
+++ b/drivers/gpu/drm/radeon/r420.c
@@ -157,31 +157,10 @@ static void r420_clock_resume(struct radeon_device *rdev)
         WREG32_PLL(R_00000D_SCLK_CNTL, sclk_cntl);
 }
 
-int r420_resume(struct radeon_device *rdev)
+static int r420_startup(struct radeon_device *rdev)
 {
         int r;
 
-        /* Make sur GART are not working */
-        if (rdev->flags & RADEON_IS_PCIE)
-                rv370_pcie_gart_disable(rdev);
-        if (rdev->flags & RADEON_IS_PCI)
-                r100_pci_gart_disable(rdev);
-        /* Resume clock before doing reset */
-        r420_clock_resume(rdev);
-        /* Reset gpu before posting otherwise ATOM will enter infinite loop */
-        if (radeon_gpu_reset(rdev)) {
-                dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
-                        RREG32(R_000E40_RBBM_STATUS),
-                        RREG32(R_0007C0_CP_STAT));
-        }
-        /* check if cards are posted or not */
-        if (rdev->is_atom_bios) {
-                atom_asic_init(rdev->mode_info.atom_context);
-        } else {
-                radeon_combios_asic_init(rdev->ddev);
-        }
-        /* Resume clock after posting */
-        r420_clock_resume(rdev);
         r300_mc_program(rdev);
         /* Initialize GART (initialize after TTM so we can allocate
          * memory through TTM but finalize after TTM) */
@@ -217,6 +196,33 @@ int r420_resume(struct radeon_device *rdev)
         return 0;
 }
 
+int r420_resume(struct radeon_device *rdev)
+{
+        /* Make sur GART are not working */
+        if (rdev->flags & RADEON_IS_PCIE)
+                rv370_pcie_gart_disable(rdev);
+        if (rdev->flags & RADEON_IS_PCI)
+                r100_pci_gart_disable(rdev);
+        /* Resume clock before doing reset */
+        r420_clock_resume(rdev);
+        /* Reset gpu before posting otherwise ATOM will enter infinite loop */
+        if (radeon_gpu_reset(rdev)) {
+                dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
+                        RREG32(R_000E40_RBBM_STATUS),
+                        RREG32(R_0007C0_CP_STAT));
+        }
+        /* check if cards are posted or not */
+        if (rdev->is_atom_bios) {
+                atom_asic_init(rdev->mode_info.atom_context);
+        } else {
+                radeon_combios_asic_init(rdev->ddev);
+        }
+        /* Resume clock after posting */
+        r420_clock_resume(rdev);
+
+        return r420_startup(rdev);
+}
+
 int r420_suspend(struct radeon_device *rdev)
 {
         r100_cp_disable(rdev);
@@ -330,7 +336,7 @@ int r420_init(struct radeon_device *rdev)
         }
         r300_set_reg_safe(rdev);
         rdev->accel_working = true;
-        r = r420_resume(rdev);
+        r = r420_startup(rdev);
         if (r) {
                 /* Somethings want wront with the accel init stop accel */
                 dev_err(rdev->dev, "Disabling GPU acceleration\n");