Merge branch 'drm-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6

* 'drm-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6: (35 commits)
  drm/radeon/kms: add definitions for v4 power tables
  drm/radeon/kms: never combine LVDS with another encoder
  drm/radeon/kms: Check module arguments to be valid V2
  drm/radeon/kms: Avoid crash when trying to cleanup uninitialized structure
  drm/radeon/kms: add cvt mode if we only have lvds w/h and no edid (v4)
  drm/radeon/kms: add 3DC compression support
  drm/radeon/kms: allow rendering while no colorbuffer is set on r300
  drm/radeon/kms: enable memory clock reading on legacy (V2)
  drm/radeon/kms: prevent parallel AtomBIOS calls
  drm/radeon/kms: set proper default tv standard
  drm/radeon/kms: fix legacy rmx
  drm/radeon/kms/atom: fill in proper defines for digital setup
  drm/kms: silencing a false positive warning.
  drm/mm: fix logic for selection of best fit block
  drm/vmwgfx: Use TTM handles instead of SIDs as user-space surface handles.
  drm/vmwgfx: Return -ERESTARTSYS when interrupted by a signal.
  drm/vmwgfx: Fix unlocked ioctl and add proper access control
  drm/radeon: fix build on 64-bit with some compilers.
  drivers/gpu: Use kzalloc for allocating only one thing
  DRM: Rename clamp variable
  ...

1 files changed, 30 insertions, 0 deletions

diff --git a/drivers/gpu/drm/radeon/r300.c b/drivers/gpu/drm/radeon/r300.c
index 83490c2b5061..3f2cc9e2e8d9 100644
--- a/drivers/gpu/drm/radeon/r300.c
+++ b/drivers/gpu/drm/radeon/r300.c
@@ -887,6 +887,14 @@ static int r300_packet0_check(struct radeon_cs_parser *p,
                         track->textures[i].cpp = 1;
                         track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
                         break;
+                case R300_TX_FORMAT_ATI2N:
+                        if (p->rdev->family < CHIP_R420) {
+                                DRM_ERROR("Invalid texture format %u\n",
+                                          (idx_value & 0x1F));
+                                return -EINVAL;
+                        }
+                        /* The same rules apply as for DXT3/5. */
+                        /* Pass through. */
                 case R300_TX_FORMAT_DXT3:
                 case R300_TX_FORMAT_DXT5:
                         track->textures[i].cpp = 1;
@@ -951,6 +959,16 @@ static int r300_packet0_check(struct radeon_cs_parser *p,
                         track->textures[i].width_11 = tmp;
                         tmp = ((idx_value >> 16) & 1) << 11;
                         track->textures[i].height_11 = tmp;
+
+                        /* ATI1N */
+                        if (idx_value & (1 << 14)) {
+                                /* The same rules apply as for DXT1. */
+                                track->textures[i].compress_format =
+                                        R100_TRACK_COMP_DXT1;
+                        }
+                } else if (idx_value & (1 << 14)) {
+                        DRM_ERROR("Forbidden bit TXFORMAT_MSB\n");
+                        return -EINVAL;
                 }
                 break;
         case 0x4480:
@@ -992,6 +1010,18 @@ static int r300_packet0_check(struct radeon_cs_parser *p,
                 }
                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
                 break;
+        case 0x4e0c:
+                /* RB3D_COLOR_CHANNEL_MASK */
+                track->color_channel_mask = idx_value;
+                break;
+        case 0x4d1c:
+                /* ZB_BW_CNTL */
+                track->fastfill = !!(idx_value & (1 << 2));
+                break;
+        case 0x4e04:
+                /* RB3D_BLENDCNTL */
+                track->blend_read_enable = !!(idx_value & (1 << 2));
+                break;
         case 0x4be8:
                 /* valid register only on RV530 */
                 if (p->rdev->family == CHIP_RV530)