drm/radeon/kms: Convert RS400/RS480 to new init path & fix legacy VGA (V3)

Also cleanup register specific to RS400/RS480. This patch also fix
legacy VGA register used to disable VGA access we were programming
wrong register. Now we should properly disable VGA on r100 up to
rs400 asics. Note that RS400/RS480 resume is broken, it hangs the
computer while reprogramming dynamic clock, doesn't work either
without that patch. We need to spend more time investigating this
issue. Version 2 of the patch remove dead code that was left
commented out in the previous version. Version 3 correct the
placement on IGP of the VRAM inside GPU address space to match the
stollen RAM placement of IGP.

Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

1 files changed, 15 insertions, 1 deletions

diff --git a/drivers/gpu/drm/radeon/r300.c b/drivers/gpu/drm/radeon/r300.c
index 1ebea8cc8c93..e491d40d4d54 100644
--- a/drivers/gpu/drm/radeon/r300.c
+++ b/drivers/gpu/drm/radeon/r300.c
@@ -33,6 +33,7 @@
 #include "radeon_drm.h"
 #include "r100_track.h"
 #include "r300d.h"
+#include "rv350d.h"
 
 #include "r300_reg_safe.h"
 
@@ -63,7 +64,6 @@ int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
  * Some of these functions might be used by newer ASICs.
  */
 void r300_gpu_init(struct radeon_device *rdev);
-int r300_mc_wait_for_idle(struct radeon_device *rdev);
 int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev);
 
 
@@ -1265,3 +1265,17 @@ void r300_mc_program(struct radeon_device *rdev)
                 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
         r100_mc_resume(rdev, &save);
 }
+
+void r300_clock_startup(struct radeon_device *rdev)
+{
+        u32 tmp;
+
+        if (radeon_dynclks != -1 && radeon_dynclks)
+                radeon_legacy_set_clock_gating(rdev, 1);
+        /* We need to force on some of the block */
+        tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
+        tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
+        if ((rdev->family == CHIP_RV350) || (rdev->family == CHIP_RV380))
+                tmp |= S_00000D_FORCE_VAP(1);
+        WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
+}