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authorDave Airlie <airlied@redhat.com>2009-09-01 01:25:57 -0400
committerDave Airlie <airlied@redhat.com>2009-09-07 18:54:31 -0400
commit551ebd837c75fc75df81811a18b7136c39cab487 (patch)
tree9703fd46cf9ad170012754f984375db37d2bf818 /drivers/gpu/drm/radeon/r300.c
parent11670d3c93210793562748d83502ecbef4034765 (diff)
drm/radeon/kms: add rn50/r100/r200 CS tracker.
This adds the command stream checker for the RN50, R100 and R200 cards. It stops any access to 3D registers on RN50, and does checks on buffer sizes on the r100/r200 cards. It also fixes some texture sizing checks on r300. Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/r300.c')
-rw-r--r--drivers/gpu/drm/radeon/r300.c363
1 files changed, 45 insertions, 318 deletions
diff --git a/drivers/gpu/drm/radeon/r300.c b/drivers/gpu/drm/radeon/r300.c
index 9f2460cf9dbc..33a2c557eac4 100644
--- a/drivers/gpu/drm/radeon/r300.c
+++ b/drivers/gpu/drm/radeon/r300.c
@@ -32,6 +32,7 @@
32#include "radeon.h" 32#include "radeon.h"
33#include "radeon_drm.h" 33#include "radeon_drm.h"
34#include "radeon_share.h" 34#include "radeon_share.h"
35#include "r100_track.h"
35 36
36#include "r300_reg_safe.h" 37#include "r300_reg_safe.h"
37 38
@@ -49,14 +50,10 @@ int r100_cs_packet_parse(struct radeon_cs_parser *p,
49 struct radeon_cs_packet *pkt, 50 struct radeon_cs_packet *pkt,
50 unsigned idx); 51 unsigned idx);
51int r100_cs_packet_parse_vline(struct radeon_cs_parser *p); 52int r100_cs_packet_parse_vline(struct radeon_cs_parser *p);
52int r100_cs_packet_next_reloc(struct radeon_cs_parser *p,
53 struct radeon_cs_reloc **cs_reloc);
54int r100_cs_parse_packet0(struct radeon_cs_parser *p, 53int r100_cs_parse_packet0(struct radeon_cs_parser *p,
55 struct radeon_cs_packet *pkt, 54 struct radeon_cs_packet *pkt,
56 const unsigned *auth, unsigned n, 55 const unsigned *auth, unsigned n,
57 radeon_packet0_check_t check); 56 radeon_packet0_check_t check);
58void r100_cs_dump_packet(struct radeon_cs_parser *p,
59 struct radeon_cs_packet *pkt);
60int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p, 57int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
61 struct radeon_cs_packet *pkt, 58 struct radeon_cs_packet *pkt,
62 struct radeon_object *robj); 59 struct radeon_object *robj);
@@ -706,264 +703,13 @@ int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev)
706/* 703/*
707 * CS functions 704 * CS functions
708 */ 705 */
709struct r300_cs_track_cb {
710 struct radeon_object *robj;
711 unsigned pitch;
712 unsigned cpp;
713 unsigned offset;
714};
715
716struct r300_cs_track_array {
717 struct radeon_object *robj;
718 unsigned esize;
719};
720
721struct r300_cs_track_texture {
722 struct radeon_object *robj;
723 unsigned pitch;
724 unsigned width;
725 unsigned height;
726 unsigned num_levels;
727 unsigned cpp;
728 unsigned tex_coord_type;
729 unsigned txdepth;
730 unsigned width_11;
731 unsigned height_11;
732 bool use_pitch;
733 bool enabled;
734 bool roundup_w;
735 bool roundup_h;
736};
737
738struct r300_cs_track {
739 unsigned num_cb;
740 unsigned maxy;
741 unsigned vtx_size;
742 unsigned vap_vf_cntl;
743 unsigned immd_dwords;
744 unsigned num_arrays;
745 unsigned max_indx;
746 struct r300_cs_track_array arrays[11];
747 struct r300_cs_track_cb cb[4];
748 struct r300_cs_track_cb zb;
749 struct r300_cs_track_texture textures[16];
750 bool z_enabled;
751};
752
753static inline void r300_cs_track_texture_print(struct r300_cs_track_texture *t)
754{
755 DRM_ERROR("pitch %d\n", t->pitch);
756 DRM_ERROR("width %d\n", t->width);
757 DRM_ERROR("height %d\n", t->height);
758 DRM_ERROR("num levels %d\n", t->num_levels);
759 DRM_ERROR("depth %d\n", t->txdepth);
760 DRM_ERROR("bpp %d\n", t->cpp);
761 DRM_ERROR("coordinate type %d\n", t->tex_coord_type);
762 DRM_ERROR("width round to power of 2 %d\n", t->roundup_w);
763 DRM_ERROR("height round to power of 2 %d\n", t->roundup_h);
764}
765
766static inline int r300_cs_track_texture_check(struct radeon_device *rdev,
767 struct r300_cs_track *track)
768{
769 struct radeon_object *robj;
770 unsigned long size;
771 unsigned u, i, w, h;
772
773 for (u = 0; u < 16; u++) {
774 if (!track->textures[u].enabled)
775 continue;
776 robj = track->textures[u].robj;
777 if (robj == NULL) {
778 DRM_ERROR("No texture bound to unit %u\n", u);
779 return -EINVAL;
780 }
781 size = 0;
782 for (i = 0; i <= track->textures[u].num_levels; i++) {
783 if (track->textures[u].use_pitch) {
784 w = track->textures[u].pitch / (1 << i);
785 } else {
786 w = track->textures[u].width / (1 << i);
787 if (rdev->family >= CHIP_RV515)
788 w |= track->textures[u].width_11;
789 if (track->textures[u].roundup_w)
790 w = roundup_pow_of_two(w);
791 }
792 h = track->textures[u].height / (1 << i);
793 if (rdev->family >= CHIP_RV515)
794 h |= track->textures[u].height_11;
795 if (track->textures[u].roundup_h)
796 h = roundup_pow_of_two(h);
797 size += w * h;
798 }
799 size *= track->textures[u].cpp;
800 switch (track->textures[u].tex_coord_type) {
801 case 0:
802 break;
803 case 1:
804 size *= (1 << track->textures[u].txdepth);
805 break;
806 case 2:
807 size *= 6;
808 break;
809 default:
810 DRM_ERROR("Invalid texture coordinate type %u for unit "
811 "%u\n", track->textures[u].tex_coord_type, u);
812 return -EINVAL;
813 }
814 if (size > radeon_object_size(robj)) {
815 DRM_ERROR("Texture of unit %u needs %lu bytes but is "
816 "%lu\n", u, size, radeon_object_size(robj));
817 r300_cs_track_texture_print(&track->textures[u]);
818 return -EINVAL;
819 }
820 }
821 return 0;
822}
823
824int r300_cs_track_check(struct radeon_device *rdev, struct r300_cs_track *track)
825{
826 unsigned i;
827 unsigned long size;
828 unsigned prim_walk;
829 unsigned nverts;
830
831 for (i = 0; i < track->num_cb; i++) {
832 if (track->cb[i].robj == NULL) {
833 DRM_ERROR("[drm] No buffer for color buffer %d !\n", i);
834 return -EINVAL;
835 }
836 size = track->cb[i].pitch * track->cb[i].cpp * track->maxy;
837 size += track->cb[i].offset;
838 if (size > radeon_object_size(track->cb[i].robj)) {
839 DRM_ERROR("[drm] Buffer too small for color buffer %d "
840 "(need %lu have %lu) !\n", i, size,
841 radeon_object_size(track->cb[i].robj));
842 DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n",
843 i, track->cb[i].pitch, track->cb[i].cpp,
844 track->cb[i].offset, track->maxy);
845 return -EINVAL;
846 }
847 }
848 if (track->z_enabled) {
849 if (track->zb.robj == NULL) {
850 DRM_ERROR("[drm] No buffer for z buffer !\n");
851 return -EINVAL;
852 }
853 size = track->zb.pitch * track->zb.cpp * track->maxy;
854 size += track->zb.offset;
855 if (size > radeon_object_size(track->zb.robj)) {
856 DRM_ERROR("[drm] Buffer too small for z buffer "
857 "(need %lu have %lu) !\n", size,
858 radeon_object_size(track->zb.robj));
859 return -EINVAL;
860 }
861 }
862 prim_walk = (track->vap_vf_cntl >> 4) & 0x3;
863 nverts = (track->vap_vf_cntl >> 16) & 0xFFFF;
864 switch (prim_walk) {
865 case 1:
866 for (i = 0; i < track->num_arrays; i++) {
867 size = track->arrays[i].esize * track->max_indx * 4;
868 if (track->arrays[i].robj == NULL) {
869 DRM_ERROR("(PW %u) Vertex array %u no buffer "
870 "bound\n", prim_walk, i);
871 return -EINVAL;
872 }
873 if (size > radeon_object_size(track->arrays[i].robj)) {
874 DRM_ERROR("(PW %u) Vertex array %u need %lu dwords "
875 "have %lu dwords\n", prim_walk, i,
876 size >> 2,
877 radeon_object_size(track->arrays[i].robj) >> 2);
878 DRM_ERROR("Max indices %u\n", track->max_indx);
879 return -EINVAL;
880 }
881 }
882 break;
883 case 2:
884 for (i = 0; i < track->num_arrays; i++) {
885 size = track->arrays[i].esize * (nverts - 1) * 4;
886 if (track->arrays[i].robj == NULL) {
887 DRM_ERROR("(PW %u) Vertex array %u no buffer "
888 "bound\n", prim_walk, i);
889 return -EINVAL;
890 }
891 if (size > radeon_object_size(track->arrays[i].robj)) {
892 DRM_ERROR("(PW %u) Vertex array %u need %lu dwords "
893 "have %lu dwords\n", prim_walk, i, size >> 2,
894 radeon_object_size(track->arrays[i].robj) >> 2);
895 return -EINVAL;
896 }
897 }
898 break;
899 case 3:
900 size = track->vtx_size * nverts;
901 if (size != track->immd_dwords) {
902 DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n",
903 track->immd_dwords, size);
904 DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n",
905 nverts, track->vtx_size);
906 return -EINVAL;
907 }
908 break;
909 default:
910 DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n",
911 prim_walk);
912 return -EINVAL;
913 }
914 return r300_cs_track_texture_check(rdev, track);
915}
916
917static inline void r300_cs_track_clear(struct r300_cs_track *track)
918{
919 unsigned i;
920
921 track->num_cb = 4;
922 track->maxy = 4096;
923 for (i = 0; i < track->num_cb; i++) {
924 track->cb[i].robj = NULL;
925 track->cb[i].pitch = 8192;
926 track->cb[i].cpp = 16;
927 track->cb[i].offset = 0;
928 }
929 track->z_enabled = true;
930 track->zb.robj = NULL;
931 track->zb.pitch = 8192;
932 track->zb.cpp = 4;
933 track->zb.offset = 0;
934 track->vtx_size = 0x7F;
935 track->immd_dwords = 0xFFFFFFFFUL;
936 track->num_arrays = 11;
937 track->max_indx = 0x00FFFFFFUL;
938 for (i = 0; i < track->num_arrays; i++) {
939 track->arrays[i].robj = NULL;
940 track->arrays[i].esize = 0x7F;
941 }
942 for (i = 0; i < 16; i++) {
943 track->textures[i].pitch = 16536;
944 track->textures[i].width = 16536;
945 track->textures[i].height = 16536;
946 track->textures[i].width_11 = 1 << 11;
947 track->textures[i].height_11 = 1 << 11;
948 track->textures[i].num_levels = 12;
949 track->textures[i].txdepth = 16;
950 track->textures[i].cpp = 64;
951 track->textures[i].tex_coord_type = 1;
952 track->textures[i].robj = NULL;
953 /* CS IB emission code makes sure texture unit are disabled */
954 track->textures[i].enabled = false;
955 track->textures[i].roundup_w = true;
956 track->textures[i].roundup_h = true;
957 }
958}
959
960static int r300_packet0_check(struct radeon_cs_parser *p, 706static int r300_packet0_check(struct radeon_cs_parser *p,
961 struct radeon_cs_packet *pkt, 707 struct radeon_cs_packet *pkt,
962 unsigned idx, unsigned reg) 708 unsigned idx, unsigned reg)
963{ 709{
964 struct radeon_cs_chunk *ib_chunk; 710 struct radeon_cs_chunk *ib_chunk;
965 struct radeon_cs_reloc *reloc; 711 struct radeon_cs_reloc *reloc;
966 struct r300_cs_track *track; 712 struct r100_cs_track *track;
967 volatile uint32_t *ib; 713 volatile uint32_t *ib;
968 uint32_t tmp, tile_flags = 0; 714 uint32_t tmp, tile_flags = 0;
969 unsigned i; 715 unsigned i;
@@ -971,7 +717,7 @@ static int r300_packet0_check(struct radeon_cs_parser *p,
971 717
972 ib = p->ib->ptr; 718 ib = p->ib->ptr;
973 ib_chunk = &p->chunks[p->chunk_ib_idx]; 719 ib_chunk = &p->chunks[p->chunk_ib_idx];
974 track = (struct r300_cs_track*)p->track; 720 track = (struct r100_cs_track *)p->track;
975 switch(reg) { 721 switch(reg) {
976 case AVIVO_D1MODE_VLINE_START_END: 722 case AVIVO_D1MODE_VLINE_START_END:
977 case RADEON_CRTC_GUI_TRIG_VLINE: 723 case RADEON_CRTC_GUI_TRIG_VLINE:
@@ -985,28 +731,9 @@ static int r300_packet0_check(struct radeon_cs_parser *p,
985 break; 731 break;
986 case RADEON_DST_PITCH_OFFSET: 732 case RADEON_DST_PITCH_OFFSET:
987 case RADEON_SRC_PITCH_OFFSET: 733 case RADEON_SRC_PITCH_OFFSET:
988 r = r100_cs_packet_next_reloc(p, &reloc); 734 r = r100_reloc_pitch_offset(p, pkt, idx, reg);
989 if (r) { 735 if (r)
990 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
991 idx, reg);
992 r100_cs_dump_packet(p, pkt);
993 return r; 736 return r;
994 }
995 tmp = ib_chunk->kdata[idx] & 0x003fffff;
996 tmp += (((u32)reloc->lobj.gpu_offset) >> 10);
997
998 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
999 tile_flags |= RADEON_DST_TILE_MACRO;
1000 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) {
1001 if (reg == RADEON_SRC_PITCH_OFFSET) {
1002 DRM_ERROR("Cannot src blit from microtiled surface\n");
1003 r100_cs_dump_packet(p, pkt);
1004 return -EINVAL;
1005 }
1006 tile_flags |= RADEON_DST_TILE_MICRO;
1007 }
1008 tmp |= tile_flags;
1009 ib[idx] = (ib_chunk->kdata[idx] & 0x3fc00000) | tmp;
1010 break; 737 break;
1011 case R300_RB3D_COLOROFFSET0: 738 case R300_RB3D_COLOROFFSET0:
1012 case R300_RB3D_COLOROFFSET1: 739 case R300_RB3D_COLOROFFSET1:
@@ -1215,42 +942,41 @@ static int r300_packet0_check(struct radeon_cs_parser *p,
1215 tmp = (ib_chunk->kdata[idx] >> 25) & 0x3; 942 tmp = (ib_chunk->kdata[idx] >> 25) & 0x3;
1216 track->textures[i].tex_coord_type = tmp; 943 track->textures[i].tex_coord_type = tmp;
1217 switch ((ib_chunk->kdata[idx] & 0x1F)) { 944 switch ((ib_chunk->kdata[idx] & 0x1F)) {
1218 case 0: 945 case R300_TX_FORMAT_X8:
1219 case 2: 946 case R300_TX_FORMAT_Y4X4:
1220 case 5: 947 case R300_TX_FORMAT_Z3Y3X2:
1221 case 18:
1222 case 20:
1223 case 21:
1224 track->textures[i].cpp = 1; 948 track->textures[i].cpp = 1;
1225 break; 949 break;
1226 case 1: 950 case R300_TX_FORMAT_X16:
1227 case 3: 951 case R300_TX_FORMAT_Y8X8:
1228 case 6: 952 case R300_TX_FORMAT_Z5Y6X5:
1229 case 7: 953 case R300_TX_FORMAT_Z6Y5X5:
1230 case 10: 954 case R300_TX_FORMAT_W4Z4Y4X4:
1231 case 11: 955 case R300_TX_FORMAT_W1Z5Y5X5:
1232 case 19: 956 case R300_TX_FORMAT_DXT1:
1233 case 22: 957 case R300_TX_FORMAT_D3DMFT_CxV8U8:
1234 case 24: 958 case R300_TX_FORMAT_B8G8_B8G8:
959 case R300_TX_FORMAT_G8R8_G8B8:
1235 track->textures[i].cpp = 2; 960 track->textures[i].cpp = 2;
1236 break; 961 break;
1237 case 4: 962 case R300_TX_FORMAT_Y16X16:
1238 case 8: 963 case R300_TX_FORMAT_Z11Y11X10:
1239 case 9: 964 case R300_TX_FORMAT_Z10Y11X11:
1240 case 12: 965 case R300_TX_FORMAT_W8Z8Y8X8:
1241 case 13: 966 case R300_TX_FORMAT_W2Z10Y10X10:
1242 case 23: 967 case 0x17:
1243 case 25: 968 case R300_TX_FORMAT_FL_I32:
1244 case 27: 969 case 0x1e:
1245 case 30: 970 case R300_TX_FORMAT_DXT3:
971 case R300_TX_FORMAT_DXT5:
1246 track->textures[i].cpp = 4; 972 track->textures[i].cpp = 4;
1247 break; 973 break;
1248 case 14: 974 case R300_TX_FORMAT_W16Z16Y16X16:
1249 case 26: 975 case R300_TX_FORMAT_FL_R16G16B16A16:
1250 case 28: 976 case R300_TX_FORMAT_FL_I32A32:
1251 track->textures[i].cpp = 8; 977 track->textures[i].cpp = 8;
1252 break; 978 break;
1253 case 29: 979 case R300_TX_FORMAT_FL_R32G32B32A32:
1254 track->textures[i].cpp = 16; 980 track->textures[i].cpp = 16;
1255 break; 981 break;
1256 default: 982 default:
@@ -1278,11 +1004,11 @@ static int r300_packet0_check(struct radeon_cs_parser *p,
1278 case 0x443C: 1004 case 0x443C:
1279 /* TX_FILTER0_[0-15] */ 1005 /* TX_FILTER0_[0-15] */
1280 i = (reg - 0x4400) >> 2; 1006 i = (reg - 0x4400) >> 2;
1281 tmp = ib_chunk->kdata[idx] & 0x7;; 1007 tmp = ib_chunk->kdata[idx] & 0x7;
1282 if (tmp == 2 || tmp == 4 || tmp == 6) { 1008 if (tmp == 2 || tmp == 4 || tmp == 6) {
1283 track->textures[i].roundup_w = false; 1009 track->textures[i].roundup_w = false;
1284 } 1010 }
1285 tmp = (ib_chunk->kdata[idx] >> 3) & 0x7;; 1011 tmp = (ib_chunk->kdata[idx] >> 3) & 0x7;
1286 if (tmp == 2 || tmp == 4 || tmp == 6) { 1012 if (tmp == 2 || tmp == 4 || tmp == 6) {
1287 track->textures[i].roundup_h = false; 1013 track->textures[i].roundup_h = false;
1288 } 1014 }
@@ -1370,8 +1096,9 @@ static int r300_packet3_check(struct radeon_cs_parser *p,
1370 struct radeon_cs_packet *pkt) 1096 struct radeon_cs_packet *pkt)
1371{ 1097{
1372 struct radeon_cs_chunk *ib_chunk; 1098 struct radeon_cs_chunk *ib_chunk;
1099
1373 struct radeon_cs_reloc *reloc; 1100 struct radeon_cs_reloc *reloc;
1374 struct r300_cs_track *track; 1101 struct r100_cs_track *track;
1375 volatile uint32_t *ib; 1102 volatile uint32_t *ib;
1376 unsigned idx; 1103 unsigned idx;
1377 unsigned i, c; 1104 unsigned i, c;
@@ -1380,7 +1107,7 @@ static int r300_packet3_check(struct radeon_cs_parser *p,
1380 ib = p->ib->ptr; 1107 ib = p->ib->ptr;
1381 ib_chunk = &p->chunks[p->chunk_ib_idx]; 1108 ib_chunk = &p->chunks[p->chunk_ib_idx];
1382 idx = pkt->idx + 1; 1109 idx = pkt->idx + 1;
1383 track = (struct r300_cs_track*)p->track; 1110 track = (struct r100_cs_track *)p->track;
1384 switch(pkt->opcode) { 1111 switch(pkt->opcode) {
1385 case PACKET3_3D_LOAD_VBPNTR: 1112 case PACKET3_3D_LOAD_VBPNTR:
1386 c = ib_chunk->kdata[idx++] & 0x1F; 1113 c = ib_chunk->kdata[idx++] & 0x1F;
@@ -1447,7 +1174,7 @@ static int r300_packet3_check(struct radeon_cs_parser *p,
1447 } 1174 }
1448 track->vap_vf_cntl = ib_chunk->kdata[idx+1]; 1175 track->vap_vf_cntl = ib_chunk->kdata[idx+1];
1449 track->immd_dwords = pkt->count - 1; 1176 track->immd_dwords = pkt->count - 1;
1450 r = r300_cs_track_check(p->rdev, track); 1177 r = r100_cs_track_check(p->rdev, track);
1451 if (r) { 1178 if (r) {
1452 return r; 1179 return r;
1453 } 1180 }
@@ -1462,35 +1189,35 @@ static int r300_packet3_check(struct radeon_cs_parser *p,
1462 } 1189 }
1463 track->vap_vf_cntl = ib_chunk->kdata[idx]; 1190 track->vap_vf_cntl = ib_chunk->kdata[idx];
1464 track->immd_dwords = pkt->count; 1191 track->immd_dwords = pkt->count;
1465 r = r300_cs_track_check(p->rdev, track); 1192 r = r100_cs_track_check(p->rdev, track);
1466 if (r) { 1193 if (r) {
1467 return r; 1194 return r;
1468 } 1195 }
1469 break; 1196 break;
1470 case PACKET3_3D_DRAW_VBUF: 1197 case PACKET3_3D_DRAW_VBUF:
1471 track->vap_vf_cntl = ib_chunk->kdata[idx + 1]; 1198 track->vap_vf_cntl = ib_chunk->kdata[idx + 1];
1472 r = r300_cs_track_check(p->rdev, track); 1199 r = r100_cs_track_check(p->rdev, track);
1473 if (r) { 1200 if (r) {
1474 return r; 1201 return r;
1475 } 1202 }
1476 break; 1203 break;
1477 case PACKET3_3D_DRAW_VBUF_2: 1204 case PACKET3_3D_DRAW_VBUF_2:
1478 track->vap_vf_cntl = ib_chunk->kdata[idx]; 1205 track->vap_vf_cntl = ib_chunk->kdata[idx];
1479 r = r300_cs_track_check(p->rdev, track); 1206 r = r100_cs_track_check(p->rdev, track);
1480 if (r) { 1207 if (r) {
1481 return r; 1208 return r;
1482 } 1209 }
1483 break; 1210 break;
1484 case PACKET3_3D_DRAW_INDX: 1211 case PACKET3_3D_DRAW_INDX:
1485 track->vap_vf_cntl = ib_chunk->kdata[idx + 1]; 1212 track->vap_vf_cntl = ib_chunk->kdata[idx + 1];
1486 r = r300_cs_track_check(p->rdev, track); 1213 r = r100_cs_track_check(p->rdev, track);
1487 if (r) { 1214 if (r) {
1488 return r; 1215 return r;
1489 } 1216 }
1490 break; 1217 break;
1491 case PACKET3_3D_DRAW_INDX_2: 1218 case PACKET3_3D_DRAW_INDX_2:
1492 track->vap_vf_cntl = ib_chunk->kdata[idx]; 1219 track->vap_vf_cntl = ib_chunk->kdata[idx];
1493 r = r300_cs_track_check(p->rdev, track); 1220 r = r100_cs_track_check(p->rdev, track);
1494 if (r) { 1221 if (r) {
1495 return r; 1222 return r;
1496 } 1223 }
@@ -1507,10 +1234,10 @@ static int r300_packet3_check(struct radeon_cs_parser *p,
1507int r300_cs_parse(struct radeon_cs_parser *p) 1234int r300_cs_parse(struct radeon_cs_parser *p)
1508{ 1235{
1509 struct radeon_cs_packet pkt; 1236 struct radeon_cs_packet pkt;
1510 struct r300_cs_track track; 1237 struct r100_cs_track track;
1511 int r; 1238 int r;
1512 1239
1513 r300_cs_track_clear(&track); 1240 r100_cs_track_clear(p->rdev, &track);
1514 p->track = &track; 1241 p->track = &track;
1515 do { 1242 do {
1516 r = r100_cs_packet_parse(p, &pkt, p->idx); 1243 r = r100_cs_packet_parse(p, &pkt, p->idx);
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-22 06:32:18 -0500