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authorMarek Olšák <maraeo@gmail.com>2009-12-17 00:02:28 -0500
committerDave Airlie <airlied@redhat.com>2009-12-22 20:14:04 -0500
commit46c64d4bfa01cda7d58c514164f8b127ab6741b7 (patch)
tree92f3439c7b761d199714cb84bf09a937582b0c6e /drivers/gpu/drm/radeon/r300.c
parent5ea597f3764880ab3a67fe2246218634a8c12778 (diff)
drm/radeon/kms: allow rendering while no colorbuffer is set on r300
Because hardware cannot disable all colorbuffers directly to do depth-only rendering, a user should: - disable reading from a colorbuffer in blending - disable fastfill - set the color channel mask to 0 to prevent writing to a colorbuffer Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/r300.c')
-rw-r--r--drivers/gpu/drm/radeon/r300.c12
1 files changed, 12 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/r300.c b/drivers/gpu/drm/radeon/r300.c
index 83490c2b5061..6a5d1177afab 100644
--- a/drivers/gpu/drm/radeon/r300.c
+++ b/drivers/gpu/drm/radeon/r300.c
@@ -992,6 +992,18 @@ static int r300_packet0_check(struct radeon_cs_parser *p,
992 } 992 }
993 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 993 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
994 break; 994 break;
995 case 0x4e0c:
996 /* RB3D_COLOR_CHANNEL_MASK */
997 track->color_channel_mask = idx_value;
998 break;
999 case 0x4d1c:
1000 /* ZB_BW_CNTL */
1001 track->fastfill = !!(idx_value & (1 << 2));
1002 break;
1003 case 0x4e04:
1004 /* RB3D_BLENDCNTL */
1005 track->blend_read_enable = !!(idx_value & (1 << 2));
1006 break;
995 case 0x4be8: 1007 case 0x4be8:
996 /* valid register only on RV530 */ 1008 /* valid register only on RV530 */
997 if (p->rdev->family == CHIP_RV530) 1009 if (p->rdev->family == CHIP_RV530)