drm/radeon: add basic zmask/hiz support (v4)

This interface allows userspace to request hyperz support, it probably
needs more locking, and really reporting that you can have hyperz is racy
since someone else might get it before you do.

v2: modify so we pass 0 valued packets to let DDX/r300c keep working.
also fixed incorrect 0x4f1c reference.

v3: fixup zb_bw_cntl so older drivers keep working

v4: add locking, fixup SC_HYPERZ_EN - patch stream to disable hiz

Signed-off-by: Dave Airlie <airlied@redhat.com>

1 files changed, 41 insertions, 3 deletions

diff --git a/drivers/gpu/drm/radeon/r300.c b/drivers/gpu/drm/radeon/r300.c
index 58eab5d47305..c827738ad7dd 100644
--- a/drivers/gpu/drm/radeon/r300.c
+++ b/drivers/gpu/drm/radeon/r300.c
@@ -1048,14 +1048,47 @@ static int r300_packet0_check(struct radeon_cs_parser *p,
                 /* RB3D_COLOR_CHANNEL_MASK */
                 track->color_channel_mask = idx_value;
                 break;
-        case 0x4d1c:
+        case 0x43a4:
+                /* SC_HYPERZ_EN */
+                /* r300c emits this register - we need to disable hyperz for it
+                 * without complaining */
+                if (p->rdev->hyperz_filp != p->filp) {
+                        if (idx_value & 0x1)
+                                ib[idx] = idx_value & ~1;
+                }
+                break;
+        case 0x4f1c:
                 /* ZB_BW_CNTL */
                 track->zb_cb_clear = !!(idx_value & (1 << 5));
+                if (p->rdev->hyperz_filp != p->filp) {
+                        if (idx_value & (R300_HIZ_ENABLE |
+                                         R300_RD_COMP_ENABLE |
+                                         R300_WR_COMP_ENABLE |
+                                         R300_FAST_FILL_ENABLE))
+                                goto fail;
+                }
                 break;
         case 0x4e04:
                 /* RB3D_BLENDCNTL */
                 track->blend_read_enable = !!(idx_value & (1 << 2));
                 break;
+        case 0x4f28: /* ZB_DEPTHCLEARVALUE */
+                break;
+        case 0x4f30: /* ZB_MASK_OFFSET */
+        case 0x4f34: /* ZB_ZMASK_PITCH */
+        case 0x4f44: /* ZB_HIZ_OFFSET */
+        case 0x4f54: /* ZB_HIZ_PITCH */
+                if (idx_value && (p->rdev->hyperz_filp != p->filp))
+                        goto fail;
+                break;
+        case 0x4028:
+                if (idx_value && (p->rdev->hyperz_filp != p->filp))
+                        goto fail;
+                /* GB_Z_PEQ_CONFIG */
+                if (p->rdev->family >= CHIP_RV350)
+                        break;
+                goto fail;
+                break;
         case 0x4be8:
                 /* valid register only on RV530 */
                 if (p->rdev->family == CHIP_RV530)
@@ -1066,8 +1099,8 @@ static int r300_packet0_check(struct radeon_cs_parser *p,
         }
         return 0;
 fail:
-        printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
-               reg, idx);
+        printk(KERN_ERR "Forbidden register 0x%04X in cs at %d (val=%08x)\n",
+               reg, idx, idx_value);
         return -EINVAL;
 }
 
@@ -1161,6 +1194,11 @@ static int r300_packet3_check(struct radeon_cs_parser *p,
                         return r;
                 }
                 break;
+        case PACKET3_3D_CLEAR_HIZ:
+        case PACKET3_3D_CLEAR_ZMASK:
+                if (p->rdev->hyperz_filp != p->filp)
+                        return -EINVAL;
+                break;
         case PACKET3_NOP:
                 break;
         default: