diff options
| author | Jerome Glisse <jglisse@redhat.com> | 2010-03-09 09:45:12 -0500 |
|---|---|---|
| committer | Dave Airlie <airlied@redhat.com> | 2010-04-05 21:21:11 -0400 |
| commit | 90aca4d2740255bd130ea71a91530b9920c70abe (patch) | |
| tree | acf9b8a4353e6727cd6cba5b71caaf9f067e465d /drivers/gpu/drm/radeon/r100d.h | |
| parent | a2d07b7438f015a0349bc9af3c96a8164549bbc5 (diff) | |
drm/radeon/kms: simplify & improve GPU reset V2
This simplify and improve GPU reset for R1XX-R6XX hw, it's
not 100% reliable here are result:
- R1XX/R2XX works bunch of time in a row, sometimes it
seems it can work indifinitly
- R3XX/R3XX the most unreliable one, sometimes you will be
able to reset few times, sometimes not even once
- R5XX more reliable than previous hw, seems to work most
of the times but once in a while it fails for no obvious
reasons (same status than previous reset just no same
happy ending)
- R6XX/R7XX are lot more reliable with this patch, still
it seems that it can fail after a bunch (reset every
2sec for 3hour bring down the GPU & computer)
This have been tested on various hw, for some odd reasons
i wasn't able to lockup RS480/RS690 (while they use to
love locking up).
Note that on R1XX-R5XX the cursor will disapear after
lockup haven't checked why, switch to console and back
to X will restore cursor.
Next step is to record the bogus command that leaded to
the lockup.
V2 Fix r6xx resume path to avoid reinitializing blit
module, use the gpu_lockup boolean to avoid entering
inifinite waiting loop on fence while reiniting the GPU
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/r100d.h')
| -rw-r--r-- | drivers/gpu/drm/radeon/r100d.h | 128 |
1 files changed, 128 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/r100d.h b/drivers/gpu/drm/radeon/r100d.h index df29a630c466..de8abd104ab7 100644 --- a/drivers/gpu/drm/radeon/r100d.h +++ b/drivers/gpu/drm/radeon/r100d.h | |||
| @@ -74,6 +74,134 @@ | |||
| 74 | #define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF) | 74 | #define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF) |
| 75 | 75 | ||
| 76 | /* Registers */ | 76 | /* Registers */ |
| 77 | #define R_0000F0_RBBM_SOFT_RESET 0x0000F0 | ||
| 78 | #define S_0000F0_SOFT_RESET_CP(x) (((x) & 0x1) << 0) | ||
| 79 | #define G_0000F0_SOFT_RESET_CP(x) (((x) >> 0) & 0x1) | ||
| 80 | #define C_0000F0_SOFT_RESET_CP 0xFFFFFFFE | ||
| 81 | #define S_0000F0_SOFT_RESET_HI(x) (((x) & 0x1) << 1) | ||
| 82 | #define G_0000F0_SOFT_RESET_HI(x) (((x) >> 1) & 0x1) | ||
| 83 | #define C_0000F0_SOFT_RESET_HI 0xFFFFFFFD | ||
| 84 | #define S_0000F0_SOFT_RESET_SE(x) (((x) & 0x1) << 2) | ||
| 85 | #define G_0000F0_SOFT_RESET_SE(x) (((x) >> 2) & 0x1) | ||
| 86 | #define C_0000F0_SOFT_RESET_SE 0xFFFFFFFB | ||
| 87 | #define S_0000F0_SOFT_RESET_RE(x) (((x) & 0x1) << 3) | ||
| 88 | #define G_0000F0_SOFT_RESET_RE(x) (((x) >> 3) & 0x1) | ||
| 89 | #define C_0000F0_SOFT_RESET_RE 0xFFFFFFF7 | ||
| 90 | #define S_0000F0_SOFT_RESET_PP(x) (((x) & 0x1) << 4) | ||
| 91 | #define G_0000F0_SOFT_RESET_PP(x) (((x) >> 4) & 0x1) | ||
| 92 | #define C_0000F0_SOFT_RESET_PP 0xFFFFFFEF | ||
| 93 | #define S_0000F0_SOFT_RESET_E2(x) (((x) & 0x1) << 5) | ||
| 94 | #define G_0000F0_SOFT_RESET_E2(x) (((x) >> 5) & 0x1) | ||
| 95 | #define C_0000F0_SOFT_RESET_E2 0xFFFFFFDF | ||
| 96 | #define S_0000F0_SOFT_RESET_RB(x) (((x) & 0x1) << 6) | ||
| 97 | #define G_0000F0_SOFT_RESET_RB(x) (((x) >> 6) & 0x1) | ||
| 98 | #define C_0000F0_SOFT_RESET_RB 0xFFFFFFBF | ||
| 99 | #define S_0000F0_SOFT_RESET_HDP(x) (((x) & 0x1) << 7) | ||
| 100 | #define G_0000F0_SOFT_RESET_HDP(x) (((x) >> 7) & 0x1) | ||
| 101 | #define C_0000F0_SOFT_RESET_HDP 0xFFFFFF7F | ||
| 102 | #define S_0000F0_SOFT_RESET_MC(x) (((x) & 0x1) << 8) | ||
| 103 | #define G_0000F0_SOFT_RESET_MC(x) (((x) >> 8) & 0x1) | ||
| 104 | #define C_0000F0_SOFT_RESET_MC 0xFFFFFEFF | ||
| 105 | #define S_0000F0_SOFT_RESET_AIC(x) (((x) & 0x1) << 9) | ||
| 106 | #define G_0000F0_SOFT_RESET_AIC(x) (((x) >> 9) & 0x1) | ||
| 107 | #define C_0000F0_SOFT_RESET_AIC 0xFFFFFDFF | ||
| 108 | #define S_0000F0_SOFT_RESET_VIP(x) (((x) & 0x1) << 10) | ||
| 109 | #define G_0000F0_SOFT_RESET_VIP(x) (((x) >> 10) & 0x1) | ||
| 110 | #define C_0000F0_SOFT_RESET_VIP 0xFFFFFBFF | ||
| 111 | #define S_0000F0_SOFT_RESET_DISP(x) (((x) & 0x1) << 11) | ||
| 112 | #define G_0000F0_SOFT_RESET_DISP(x) (((x) >> 11) & 0x1) | ||
| 113 | #define C_0000F0_SOFT_RESET_DISP 0xFFFFF7FF | ||
| 114 | #define S_0000F0_SOFT_RESET_CG(x) (((x) & 0x1) << 12) | ||
| 115 | #define G_0000F0_SOFT_RESET_CG(x) (((x) >> 12) & 0x1) | ||
| 116 | #define C_0000F0_SOFT_RESET_CG 0xFFFFEFFF | ||
| 117 | #define R_000030_BUS_CNTL 0x000030 | ||
| 118 | #define S_000030_BUS_DBL_RESYNC(x) (((x) & 0x1) << 0) | ||
| 119 | #define G_000030_BUS_DBL_RESYNC(x) (((x) >> 0) & 0x1) | ||
| 120 | #define C_000030_BUS_DBL_RESYNC 0xFFFFFFFE | ||
| 121 | #define S_000030_BUS_MSTR_RESET(x) (((x) & 0x1) << 1) | ||
| 122 | #define G_000030_BUS_MSTR_RESET(x) (((x) >> 1) & 0x1) | ||
| 123 | #define C_000030_BUS_MSTR_RESET 0xFFFFFFFD | ||
| 124 | #define S_000030_BUS_FLUSH_BUF(x) (((x) & 0x1) << 2) | ||
| 125 | #define G_000030_BUS_FLUSH_BUF(x) (((x) >> 2) & 0x1) | ||
| 126 | #define C_000030_BUS_FLUSH_BUF 0xFFFFFFFB | ||
| 127 | #define S_000030_BUS_STOP_REQ_DIS(x) (((x) & 0x1) << 3) | ||
| 128 | #define G_000030_BUS_STOP_REQ_DIS(x) (((x) >> 3) & 0x1) | ||
| 129 | #define C_000030_BUS_STOP_REQ_DIS 0xFFFFFFF7 | ||
| 130 | #define S_000030_BUS_PM4_READ_COMBINE_EN(x) (((x) & 0x1) << 4) | ||
| 131 | #define G_000030_BUS_PM4_READ_COMBINE_EN(x) (((x) >> 4) & 0x1) | ||
| 132 | #define C_000030_BUS_PM4_READ_COMBINE_EN 0xFFFFFFEF | ||
| 133 | #define S_000030_BUS_WRT_COMBINE_EN(x) (((x) & 0x1) << 5) | ||
| 134 | #define G_000030_BUS_WRT_COMBINE_EN(x) (((x) >> 5) & 0x1) | ||
| 135 | #define C_000030_BUS_WRT_COMBINE_EN 0xFFFFFFDF | ||
| 136 | #define S_000030_BUS_MASTER_DIS(x) (((x) & 0x1) << 6) | ||
| 137 | #define G_000030_BUS_MASTER_DIS(x) (((x) >> 6) & 0x1) | ||
| 138 | #define C_000030_BUS_MASTER_DIS 0xFFFFFFBF | ||
| 139 | #define S_000030_BIOS_ROM_WRT_EN(x) (((x) & 0x1) << 7) | ||
| 140 | #define G_000030_BIOS_ROM_WRT_EN(x) (((x) >> 7) & 0x1) | ||
| 141 | #define C_000030_BIOS_ROM_WRT_EN 0xFFFFFF7F | ||
| 142 | #define S_000030_BM_DAC_CRIPPLE(x) (((x) & 0x1) << 8) | ||
| 143 | #define G_000030_BM_DAC_CRIPPLE(x) (((x) >> 8) & 0x1) | ||
| 144 | #define C_000030_BM_DAC_CRIPPLE 0xFFFFFEFF | ||
| 145 | #define S_000030_BUS_NON_PM4_READ_COMBINE_EN(x) (((x) & 0x1) << 9) | ||
| 146 | #define G_000030_BUS_NON_PM4_READ_COMBINE_EN(x) (((x) >> 9) & 0x1) | ||
| 147 | #define C_000030_BUS_NON_PM4_READ_COMBINE_EN 0xFFFFFDFF | ||
| 148 | #define S_000030_BUS_XFERD_DISCARD_EN(x) (((x) & 0x1) << 10) | ||
| 149 | #define G_000030_BUS_XFERD_DISCARD_EN(x) (((x) >> 10) & 0x1) | ||
| 150 | #define C_000030_BUS_XFERD_DISCARD_EN 0xFFFFFBFF | ||
| 151 | #define S_000030_BUS_SGL_READ_DISABLE(x) (((x) & 0x1) << 11) | ||
| 152 | #define G_000030_BUS_SGL_READ_DISABLE(x) (((x) >> 11) & 0x1) | ||
| 153 | #define C_000030_BUS_SGL_READ_DISABLE 0xFFFFF7FF | ||
| 154 | #define S_000030_BIOS_DIS_ROM(x) (((x) & 0x1) << 12) | ||
| 155 | #define G_000030_BIOS_DIS_ROM(x) (((x) >> 12) & 0x1) | ||
| 156 | #define C_000030_BIOS_DIS_ROM 0xFFFFEFFF | ||
| 157 | #define S_000030_BUS_PCI_READ_RETRY_EN(x) (((x) & 0x1) << 13) | ||
| 158 | #define G_000030_BUS_PCI_READ_RETRY_EN(x) (((x) >> 13) & 0x1) | ||
| 159 | #define C_000030_BUS_PCI_READ_RETRY_EN 0xFFFFDFFF | ||
| 160 | #define S_000030_BUS_AGP_AD_STEPPING_EN(x) (((x) & 0x1) << 14) | ||
| 161 | #define G_000030_BUS_AGP_AD_STEPPING_EN(x) (((x) >> 14) & 0x1) | ||
| 162 | #define C_000030_BUS_AGP_AD_STEPPING_EN 0xFFFFBFFF | ||
| 163 | #define S_000030_BUS_PCI_WRT_RETRY_EN(x) (((x) & 0x1) << 15) | ||
| 164 | #define G_000030_BUS_PCI_WRT_RETRY_EN(x) (((x) >> 15) & 0x1) | ||
| 165 | #define C_000030_BUS_PCI_WRT_RETRY_EN 0xFFFF7FFF | ||
| 166 | #define S_000030_BUS_RETRY_WS(x) (((x) & 0xF) << 16) | ||
| 167 | #define G_000030_BUS_RETRY_WS(x) (((x) >> 16) & 0xF) | ||
| 168 | #define C_000030_BUS_RETRY_WS 0xFFF0FFFF | ||
| 169 | #define S_000030_BUS_MSTR_RD_MULT(x) (((x) & 0x1) << 20) | ||
| 170 | #define G_000030_BUS_MSTR_RD_MULT(x) (((x) >> 20) & 0x1) | ||
| 171 | #define C_000030_BUS_MSTR_RD_MULT 0xFFEFFFFF | ||
| 172 | #define S_000030_BUS_MSTR_RD_LINE(x) (((x) & 0x1) << 21) | ||
| 173 | #define G_000030_BUS_MSTR_RD_LINE(x) (((x) >> 21) & 0x1) | ||
| 174 | #define C_000030_BUS_MSTR_RD_LINE 0xFFDFFFFF | ||
| 175 | #define S_000030_BUS_SUSPEND(x) (((x) & 0x1) << 22) | ||
| 176 | #define G_000030_BUS_SUSPEND(x) (((x) >> 22) & 0x1) | ||
| 177 | #define C_000030_BUS_SUSPEND 0xFFBFFFFF | ||
| 178 | #define S_000030_LAT_16X(x) (((x) & 0x1) << 23) | ||
| 179 | #define G_000030_LAT_16X(x) (((x) >> 23) & 0x1) | ||
| 180 | #define C_000030_LAT_16X 0xFF7FFFFF | ||
| 181 | #define S_000030_BUS_RD_DISCARD_EN(x) (((x) & 0x1) << 24) | ||
| 182 | #define G_000030_BUS_RD_DISCARD_EN(x) (((x) >> 24) & 0x1) | ||
| 183 | #define C_000030_BUS_RD_DISCARD_EN 0xFEFFFFFF | ||
| 184 | #define S_000030_ENFRCWRDY(x) (((x) & 0x1) << 25) | ||
| 185 | #define G_000030_ENFRCWRDY(x) (((x) >> 25) & 0x1) | ||
| 186 | #define C_000030_ENFRCWRDY 0xFDFFFFFF | ||
| 187 | #define S_000030_BUS_MSTR_WS(x) (((x) & 0x1) << 26) | ||
| 188 | #define G_000030_BUS_MSTR_WS(x) (((x) >> 26) & 0x1) | ||
| 189 | #define C_000030_BUS_MSTR_WS 0xFBFFFFFF | ||
| 190 | #define S_000030_BUS_PARKING_DIS(x) (((x) & 0x1) << 27) | ||
| 191 | #define G_000030_BUS_PARKING_DIS(x) (((x) >> 27) & 0x1) | ||
| 192 | #define C_000030_BUS_PARKING_DIS 0xF7FFFFFF | ||
| 193 | #define S_000030_BUS_MSTR_DISCONNECT_EN(x) (((x) & 0x1) << 28) | ||
| 194 | #define G_000030_BUS_MSTR_DISCONNECT_EN(x) (((x) >> 28) & 0x1) | ||
| 195 | #define C_000030_BUS_MSTR_DISCONNECT_EN 0xEFFFFFFF | ||
| 196 | #define S_000030_SERR_EN(x) (((x) & 0x1) << 29) | ||
| 197 | #define G_000030_SERR_EN(x) (((x) >> 29) & 0x1) | ||
| 198 | #define C_000030_SERR_EN 0xDFFFFFFF | ||
| 199 | #define S_000030_BUS_READ_BURST(x) (((x) & 0x1) << 30) | ||
| 200 | #define G_000030_BUS_READ_BURST(x) (((x) >> 30) & 0x1) | ||
| 201 | #define C_000030_BUS_READ_BURST 0xBFFFFFFF | ||
| 202 | #define S_000030_BUS_RDY_READ_DLY(x) (((x) & 0x1) << 31) | ||
| 203 | #define G_000030_BUS_RDY_READ_DLY(x) (((x) >> 31) & 0x1) | ||
| 204 | #define C_000030_BUS_RDY_READ_DLY 0x7FFFFFFF | ||
| 77 | #define R_000040_GEN_INT_CNTL 0x000040 | 205 | #define R_000040_GEN_INT_CNTL 0x000040 |
| 78 | #define S_000040_CRTC_VBLANK(x) (((x) & 0x1) << 0) | 206 | #define S_000040_CRTC_VBLANK(x) (((x) & 0x1) << 0) |
| 79 | #define G_000040_CRTC_VBLANK(x) (((x) >> 0) & 0x1) | 207 | #define G_000040_CRTC_VBLANK(x) (((x) >> 0) & 0x1) |