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authorJerome Glisse <jglisse@redhat.com>2010-03-09 09:45:11 -0500
committerDave Airlie <airlied@redhat.com>2010-04-05 21:21:04 -0400
commita2d07b7438f015a0349bc9af3c96a8164549bbc5 (patch)
tree7e05f0789ab09215efc96f8d2fd49eb61c3cab9f /drivers/gpu/drm/radeon/r100.c
parent225758d8ba4fdcc1e8c9cf617fd89529bd4a9596 (diff)
drm/radeon/kms: rename gpu_reset to asic_reset
Patch rename gpu_reset to asic_reset in prevision of having gpu_reset doing more stuff than just basic asic reset. Signed-off-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/r100.c')
-rw-r--r--drivers/gpu/drm/radeon/r100.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c
index 845c8f3063fe..8bb91092bffc 100644
--- a/drivers/gpu/drm/radeon/r100.c
+++ b/drivers/gpu/drm/radeon/r100.c
@@ -1863,7 +1863,7 @@ bool r100_gpu_is_lockup(struct radeon_device *rdev)
1863 return r100_gpu_cp_is_lockup(rdev, &rdev->config.r100.lockup, &rdev->cp); 1863 return r100_gpu_cp_is_lockup(rdev, &rdev->config.r100.lockup, &rdev->cp);
1864} 1864}
1865 1865
1866int r100_gpu_reset(struct radeon_device *rdev) 1866int r100_asic_reset(struct radeon_device *rdev)
1867{ 1867{
1868 uint32_t status; 1868 uint32_t status;
1869 1869
@@ -3512,7 +3512,7 @@ int r100_resume(struct radeon_device *rdev)
3512 /* Resume clock before doing reset */ 3512 /* Resume clock before doing reset */
3513 r100_clock_startup(rdev); 3513 r100_clock_startup(rdev);
3514 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 3514 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
3515 if (radeon_gpu_reset(rdev)) { 3515 if (radeon_asic_reset(rdev)) {
3516 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 3516 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3517 RREG32(R_000E40_RBBM_STATUS), 3517 RREG32(R_000E40_RBBM_STATUS),
3518 RREG32(R_0007C0_CP_STAT)); 3518 RREG32(R_0007C0_CP_STAT));
@@ -3581,7 +3581,7 @@ int r100_init(struct radeon_device *rdev)
3581 return r; 3581 return r;
3582 } 3582 }
3583 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 3583 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
3584 if (radeon_gpu_reset(rdev)) { 3584 if (radeon_asic_reset(rdev)) {
3585 dev_warn(rdev->dev, 3585 dev_warn(rdev->dev,
3586 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 3586 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3587 RREG32(R_000E40_RBBM_STATUS), 3587 RREG32(R_000E40_RBBM_STATUS),