drm/radeon/kms: Convert RS400/RS480 to new init path & fix legacy VGA (V3)

Also cleanup register specific to RS400/RS480. This patch also fix
legacy VGA register used to disable VGA access we were programming
wrong register. Now we should properly disable VGA on r100 up to
rs400 asics. Note that RS400/RS480 resume is broken, it hangs the
computer while reprogramming dynamic clock, doesn't work either
without that patch. We need to spend more time investigating this
issue. Version 2 of the patch remove dead code that was left
commented out in the previous version. Version 3 correct the
placement on IGP of the VRAM inside GPU address space to match the
stollen RAM placement of IGP.

Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

1 files changed, 11 insertions, 3 deletions

diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c
index d2099146fc40..dc45ec1d4189 100644
--- a/drivers/gpu/drm/radeon/r100.c
+++ b/drivers/gpu/drm/radeon/r100.c
@@ -3100,7 +3100,7 @@ void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save)
         WREG32(R_000740_CP_CSQ_CNTL, 0);
 
         /* Save few CRTC registers */
-        save->GENMO_WT = RREG32(R_0003C0_GENMO_WT);
+        save->GENMO_WT = RREG8(R_0003C2_GENMO_WT);
         save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL);
         save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL);
         save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET);
@@ -3110,7 +3110,7 @@ void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save)
         }
 
         /* Disable VGA aperture access */
-        WREG32(R_0003C0_GENMO_WT, C_0003C0_VGA_RAM_EN & save->GENMO_WT);
+        WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT);
         /* Disable cursor, overlay, crtc */
         WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1));
         WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL |
@@ -3142,10 +3142,18 @@ void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save)
                                 rdev->mc.vram_location);
         }
         /* Restore CRTC registers */
-        WREG32(R_0003C0_GENMO_WT, save->GENMO_WT);
+        WREG8(R_0003C2_GENMO_WT, save->GENMO_WT);
         WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL);
         WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL);
         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
                 WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL);
         }
 }
+
+void r100_vga_render_disable(struct radeon_device *rdev)
+{
+    u32 tmp;
+
+    tmp = RREG8(R_0003C2_GENMO_WT);
+        WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp);
+}