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authorAlex Deucher <alexdeucher@gmail.com>2010-02-05 01:58:28 -0500
committerDave Airlie <airlied@redhat.com>2010-02-08 18:31:20 -0500
commit4612dc97991a09e1a9e4d5d981e16589d7cb150c (patch)
treebd307eed8985ad4e445b0b43ece3f0e076aaa86b /drivers/gpu/drm/radeon/r100.c
parent3c537889e17232e9073f75ae8710ea0f008c5a29 (diff)
drm/radeon/kms: clean up some low-hanging magic numbers
Switch some magic numbers to their proper defines. The register header madness needs to be cleaned up at some point. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/r100.c')
-rw-r--r--drivers/gpu/drm/radeon/r100.c12
1 files changed, 6 insertions, 6 deletions
diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c
index 38209a61e515..597f85b283bc 100644
--- a/drivers/gpu/drm/radeon/r100.c
+++ b/drivers/gpu/drm/radeon/r100.c
@@ -366,8 +366,8 @@ void r100_fence_ring_emit(struct radeon_device *rdev,
366 radeon_ring_write(rdev, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); 366 radeon_ring_write(rdev, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0));
367 radeon_ring_write(rdev, RADEON_RB3D_ZC_FLUSH_ALL); 367 radeon_ring_write(rdev, RADEON_RB3D_ZC_FLUSH_ALL);
368 /* Wait until IDLE & CLEAN */ 368 /* Wait until IDLE & CLEAN */
369 radeon_ring_write(rdev, PACKET0(0x1720, 0)); 369 radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
370 radeon_ring_write(rdev, (1 << 16) | (1 << 17)); 370 radeon_ring_write(rdev, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN);
371 radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0)); 371 radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
372 radeon_ring_write(rdev, rdev->config.r100.hdp_cntl | 372 radeon_ring_write(rdev, rdev->config.r100.hdp_cntl |
373 RADEON_HDP_READ_BUFFER_INVALIDATE); 373 RADEON_HDP_READ_BUFFER_INVALIDATE);
@@ -1701,7 +1701,7 @@ int r100_gui_wait_for_idle(struct radeon_device *rdev)
1701 } 1701 }
1702 for (i = 0; i < rdev->usec_timeout; i++) { 1702 for (i = 0; i < rdev->usec_timeout; i++) {
1703 tmp = RREG32(RADEON_RBBM_STATUS); 1703 tmp = RREG32(RADEON_RBBM_STATUS);
1704 if (!(tmp & (1 << 31))) { 1704 if (!(tmp & RADEON_RBBM_ACTIVE)) {
1705 return 0; 1705 return 0;
1706 } 1706 }
1707 DRM_UDELAY(1); 1707 DRM_UDELAY(1);
@@ -1716,8 +1716,8 @@ int r100_mc_wait_for_idle(struct radeon_device *rdev)
1716 1716
1717 for (i = 0; i < rdev->usec_timeout; i++) { 1717 for (i = 0; i < rdev->usec_timeout; i++) {
1718 /* read MC_STATUS */ 1718 /* read MC_STATUS */
1719 tmp = RREG32(0x0150); 1719 tmp = RREG32(RADEON_MC_STATUS);
1720 if (tmp & (1 << 2)) { 1720 if (tmp & RADEON_MC_IDLE) {
1721 return 0; 1721 return 0;
1722 } 1722 }
1723 DRM_UDELAY(1); 1723 DRM_UDELAY(1);
@@ -1790,7 +1790,7 @@ int r100_gpu_reset(struct radeon_device *rdev)
1790 } 1790 }
1791 /* Check if GPU is idle */ 1791 /* Check if GPU is idle */
1792 status = RREG32(RADEON_RBBM_STATUS); 1792 status = RREG32(RADEON_RBBM_STATUS);
1793 if (status & (1 << 31)) { 1793 if (status & RADEON_RBBM_ACTIVE) {
1794 DRM_ERROR("Failed to reset GPU (RBBM_STATUS=0x%08X)\n", status); 1794 DRM_ERROR("Failed to reset GPU (RBBM_STATUS=0x%08X)\n", status);
1795 return -1; 1795 return -1;
1796 } 1796 }