diff options
author | Ilija Hadzic <ihadzic@research.bell-labs.com> | 2013-01-02 18:27:47 -0500 |
---|---|---|
committer | Alex Deucher <alexander.deucher@amd.com> | 2013-01-31 16:24:45 -0500 |
commit | 012e976d42d2819c79bdd4ef2843515bdd44e408 (patch) | |
tree | c4867ae6fdca55954685ce6a194bc41e6d4e330b /drivers/gpu/drm/radeon/r100.c | |
parent | e97169930941c4326dd563578369590a52aec707 (diff) |
drm/radeon: use common next_reloc function
This patch eliminates ASIC-specific ***_cs_packet_next_reloc
functions and hooks up the new common function.
Signed-off-by: Ilija Hadzic <ihadzic@research.bell-labs.com>
Reviewed-by: Marek Olšák <maraeo@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/r100.c')
-rw-r--r-- | drivers/gpu/drm/radeon/r100.c | 76 |
1 files changed, 14 insertions, 62 deletions
diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c index cf7e35903eae..846960764a05 100644 --- a/drivers/gpu/drm/radeon/r100.c +++ b/drivers/gpu/drm/radeon/r100.c | |||
@@ -1215,7 +1215,7 @@ int r100_reloc_pitch_offset(struct radeon_cs_parser *p, | |||
1215 | struct radeon_cs_reloc *reloc; | 1215 | struct radeon_cs_reloc *reloc; |
1216 | u32 value; | 1216 | u32 value; |
1217 | 1217 | ||
1218 | r = r100_cs_packet_next_reloc(p, &reloc); | 1218 | r = radeon_cs_packet_next_reloc(p, &reloc, 0); |
1219 | if (r) { | 1219 | if (r) { |
1220 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", | 1220 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
1221 | idx, reg); | 1221 | idx, reg); |
@@ -1268,7 +1268,7 @@ int r100_packet3_load_vbpntr(struct radeon_cs_parser *p, | |||
1268 | } | 1268 | } |
1269 | track->num_arrays = c; | 1269 | track->num_arrays = c; |
1270 | for (i = 0; i < (c - 1); i+=2, idx+=3) { | 1270 | for (i = 0; i < (c - 1); i+=2, idx+=3) { |
1271 | r = r100_cs_packet_next_reloc(p, &reloc); | 1271 | r = radeon_cs_packet_next_reloc(p, &reloc, 0); |
1272 | if (r) { | 1272 | if (r) { |
1273 | DRM_ERROR("No reloc for packet3 %d\n", | 1273 | DRM_ERROR("No reloc for packet3 %d\n", |
1274 | pkt->opcode); | 1274 | pkt->opcode); |
@@ -1281,7 +1281,7 @@ int r100_packet3_load_vbpntr(struct radeon_cs_parser *p, | |||
1281 | track->arrays[i + 0].esize = idx_value >> 8; | 1281 | track->arrays[i + 0].esize = idx_value >> 8; |
1282 | track->arrays[i + 0].robj = reloc->robj; | 1282 | track->arrays[i + 0].robj = reloc->robj; |
1283 | track->arrays[i + 0].esize &= 0x7F; | 1283 | track->arrays[i + 0].esize &= 0x7F; |
1284 | r = r100_cs_packet_next_reloc(p, &reloc); | 1284 | r = radeon_cs_packet_next_reloc(p, &reloc, 0); |
1285 | if (r) { | 1285 | if (r) { |
1286 | DRM_ERROR("No reloc for packet3 %d\n", | 1286 | DRM_ERROR("No reloc for packet3 %d\n", |
1287 | pkt->opcode); | 1287 | pkt->opcode); |
@@ -1294,7 +1294,7 @@ int r100_packet3_load_vbpntr(struct radeon_cs_parser *p, | |||
1294 | track->arrays[i + 1].esize &= 0x7F; | 1294 | track->arrays[i + 1].esize &= 0x7F; |
1295 | } | 1295 | } |
1296 | if (c & 1) { | 1296 | if (c & 1) { |
1297 | r = r100_cs_packet_next_reloc(p, &reloc); | 1297 | r = radeon_cs_packet_next_reloc(p, &reloc, 0); |
1298 | if (r) { | 1298 | if (r) { |
1299 | DRM_ERROR("No reloc for packet3 %d\n", | 1299 | DRM_ERROR("No reloc for packet3 %d\n", |
1300 | pkt->opcode); | 1300 | pkt->opcode); |
@@ -1445,54 +1445,6 @@ int r100_cs_packet_parse_vline(struct radeon_cs_parser *p) | |||
1445 | return 0; | 1445 | return 0; |
1446 | } | 1446 | } |
1447 | 1447 | ||
1448 | /** | ||
1449 | * r100_cs_packet_next_reloc() - parse next packet which should be reloc packet3 | ||
1450 | * @parser: parser structure holding parsing context. | ||
1451 | * @data: pointer to relocation data | ||
1452 | * @offset_start: starting offset | ||
1453 | * @offset_mask: offset mask (to align start offset on) | ||
1454 | * @reloc: reloc informations | ||
1455 | * | ||
1456 | * Check next packet is relocation packet3, do bo validation and compute | ||
1457 | * GPU offset using the provided start. | ||
1458 | **/ | ||
1459 | int r100_cs_packet_next_reloc(struct radeon_cs_parser *p, | ||
1460 | struct radeon_cs_reloc **cs_reloc) | ||
1461 | { | ||
1462 | struct radeon_cs_chunk *relocs_chunk; | ||
1463 | struct radeon_cs_packet p3reloc; | ||
1464 | unsigned idx; | ||
1465 | int r; | ||
1466 | |||
1467 | if (p->chunk_relocs_idx == -1) { | ||
1468 | DRM_ERROR("No relocation chunk !\n"); | ||
1469 | return -EINVAL; | ||
1470 | } | ||
1471 | *cs_reloc = NULL; | ||
1472 | relocs_chunk = &p->chunks[p->chunk_relocs_idx]; | ||
1473 | r = radeon_cs_packet_parse(p, &p3reloc, p->idx); | ||
1474 | if (r) { | ||
1475 | return r; | ||
1476 | } | ||
1477 | p->idx += p3reloc.count + 2; | ||
1478 | if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) { | ||
1479 | DRM_ERROR("No packet3 for relocation for packet at %d.\n", | ||
1480 | p3reloc.idx); | ||
1481 | radeon_cs_dump_packet(p, &p3reloc); | ||
1482 | return -EINVAL; | ||
1483 | } | ||
1484 | idx = radeon_get_ib_value(p, p3reloc.idx + 1); | ||
1485 | if (idx >= relocs_chunk->length_dw) { | ||
1486 | DRM_ERROR("Relocs at %d after relocations chunk end %d !\n", | ||
1487 | idx, relocs_chunk->length_dw); | ||
1488 | radeon_cs_dump_packet(p, &p3reloc); | ||
1489 | return -EINVAL; | ||
1490 | } | ||
1491 | /* FIXME: we assume reloc size is 4 dwords */ | ||
1492 | *cs_reloc = p->relocs_ptr[(idx / 4)]; | ||
1493 | return 0; | ||
1494 | } | ||
1495 | |||
1496 | static int r100_get_vtx_size(uint32_t vtx_fmt) | 1448 | static int r100_get_vtx_size(uint32_t vtx_fmt) |
1497 | { | 1449 | { |
1498 | int vtx_size; | 1450 | int vtx_size; |
@@ -1583,7 +1535,7 @@ static int r100_packet0_check(struct radeon_cs_parser *p, | |||
1583 | return r; | 1535 | return r; |
1584 | break; | 1536 | break; |
1585 | case RADEON_RB3D_DEPTHOFFSET: | 1537 | case RADEON_RB3D_DEPTHOFFSET: |
1586 | r = r100_cs_packet_next_reloc(p, &reloc); | 1538 | r = radeon_cs_packet_next_reloc(p, &reloc, 0); |
1587 | if (r) { | 1539 | if (r) { |
1588 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", | 1540 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
1589 | idx, reg); | 1541 | idx, reg); |
@@ -1596,7 +1548,7 @@ static int r100_packet0_check(struct radeon_cs_parser *p, | |||
1596 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); | 1548 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
1597 | break; | 1549 | break; |
1598 | case RADEON_RB3D_COLOROFFSET: | 1550 | case RADEON_RB3D_COLOROFFSET: |
1599 | r = r100_cs_packet_next_reloc(p, &reloc); | 1551 | r = radeon_cs_packet_next_reloc(p, &reloc, 0); |
1600 | if (r) { | 1552 | if (r) { |
1601 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", | 1553 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
1602 | idx, reg); | 1554 | idx, reg); |
@@ -1612,7 +1564,7 @@ static int r100_packet0_check(struct radeon_cs_parser *p, | |||
1612 | case RADEON_PP_TXOFFSET_1: | 1564 | case RADEON_PP_TXOFFSET_1: |
1613 | case RADEON_PP_TXOFFSET_2: | 1565 | case RADEON_PP_TXOFFSET_2: |
1614 | i = (reg - RADEON_PP_TXOFFSET_0) / 24; | 1566 | i = (reg - RADEON_PP_TXOFFSET_0) / 24; |
1615 | r = r100_cs_packet_next_reloc(p, &reloc); | 1567 | r = radeon_cs_packet_next_reloc(p, &reloc, 0); |
1616 | if (r) { | 1568 | if (r) { |
1617 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", | 1569 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
1618 | idx, reg); | 1570 | idx, reg); |
@@ -1639,7 +1591,7 @@ static int r100_packet0_check(struct radeon_cs_parser *p, | |||
1639 | case RADEON_PP_CUBIC_OFFSET_T0_3: | 1591 | case RADEON_PP_CUBIC_OFFSET_T0_3: |
1640 | case RADEON_PP_CUBIC_OFFSET_T0_4: | 1592 | case RADEON_PP_CUBIC_OFFSET_T0_4: |
1641 | i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4; | 1593 | i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4; |
1642 | r = r100_cs_packet_next_reloc(p, &reloc); | 1594 | r = radeon_cs_packet_next_reloc(p, &reloc, 0); |
1643 | if (r) { | 1595 | if (r) { |
1644 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", | 1596 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
1645 | idx, reg); | 1597 | idx, reg); |
@@ -1657,7 +1609,7 @@ static int r100_packet0_check(struct radeon_cs_parser *p, | |||
1657 | case RADEON_PP_CUBIC_OFFSET_T1_3: | 1609 | case RADEON_PP_CUBIC_OFFSET_T1_3: |
1658 | case RADEON_PP_CUBIC_OFFSET_T1_4: | 1610 | case RADEON_PP_CUBIC_OFFSET_T1_4: |
1659 | i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4; | 1611 | i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4; |
1660 | r = r100_cs_packet_next_reloc(p, &reloc); | 1612 | r = radeon_cs_packet_next_reloc(p, &reloc, 0); |
1661 | if (r) { | 1613 | if (r) { |
1662 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", | 1614 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
1663 | idx, reg); | 1615 | idx, reg); |
@@ -1675,7 +1627,7 @@ static int r100_packet0_check(struct radeon_cs_parser *p, | |||
1675 | case RADEON_PP_CUBIC_OFFSET_T2_3: | 1627 | case RADEON_PP_CUBIC_OFFSET_T2_3: |
1676 | case RADEON_PP_CUBIC_OFFSET_T2_4: | 1628 | case RADEON_PP_CUBIC_OFFSET_T2_4: |
1677 | i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4; | 1629 | i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4; |
1678 | r = r100_cs_packet_next_reloc(p, &reloc); | 1630 | r = radeon_cs_packet_next_reloc(p, &reloc, 0); |
1679 | if (r) { | 1631 | if (r) { |
1680 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", | 1632 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
1681 | idx, reg); | 1633 | idx, reg); |
@@ -1693,7 +1645,7 @@ static int r100_packet0_check(struct radeon_cs_parser *p, | |||
1693 | track->zb_dirty = true; | 1645 | track->zb_dirty = true; |
1694 | break; | 1646 | break; |
1695 | case RADEON_RB3D_COLORPITCH: | 1647 | case RADEON_RB3D_COLORPITCH: |
1696 | r = r100_cs_packet_next_reloc(p, &reloc); | 1648 | r = radeon_cs_packet_next_reloc(p, &reloc, 0); |
1697 | if (r) { | 1649 | if (r) { |
1698 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", | 1650 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
1699 | idx, reg); | 1651 | idx, reg); |
@@ -1764,7 +1716,7 @@ static int r100_packet0_check(struct radeon_cs_parser *p, | |||
1764 | track->zb_dirty = true; | 1716 | track->zb_dirty = true; |
1765 | break; | 1717 | break; |
1766 | case RADEON_RB3D_ZPASS_ADDR: | 1718 | case RADEON_RB3D_ZPASS_ADDR: |
1767 | r = r100_cs_packet_next_reloc(p, &reloc); | 1719 | r = radeon_cs_packet_next_reloc(p, &reloc, 0); |
1768 | if (r) { | 1720 | if (r) { |
1769 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", | 1721 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
1770 | idx, reg); | 1722 | idx, reg); |
@@ -1925,7 +1877,7 @@ static int r100_packet3_check(struct radeon_cs_parser *p, | |||
1925 | return r; | 1877 | return r; |
1926 | break; | 1878 | break; |
1927 | case PACKET3_INDX_BUFFER: | 1879 | case PACKET3_INDX_BUFFER: |
1928 | r = r100_cs_packet_next_reloc(p, &reloc); | 1880 | r = radeon_cs_packet_next_reloc(p, &reloc, 0); |
1929 | if (r) { | 1881 | if (r) { |
1930 | DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode); | 1882 | DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode); |
1931 | radeon_cs_dump_packet(p, pkt); | 1883 | radeon_cs_dump_packet(p, pkt); |
@@ -1939,7 +1891,7 @@ static int r100_packet3_check(struct radeon_cs_parser *p, | |||
1939 | break; | 1891 | break; |
1940 | case 0x23: | 1892 | case 0x23: |
1941 | /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */ | 1893 | /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */ |
1942 | r = r100_cs_packet_next_reloc(p, &reloc); | 1894 | r = radeon_cs_packet_next_reloc(p, &reloc, 0); |
1943 | if (r) { | 1895 | if (r) { |
1944 | DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode); | 1896 | DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode); |
1945 | radeon_cs_dump_packet(p, pkt); | 1897 | radeon_cs_dump_packet(p, pkt); |