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authorJerome Glisse <jglisse@redhat.com>2010-08-10 17:41:31 -0400
committerDave Airlie <airlied@redhat.com>2010-10-12 06:17:43 -0400
commitc919b371cb734f42b1130e706ecee262f8d9261d (patch)
tree3044d77ddc64b7fd4b9cb7e06630235e82397fb4 /drivers/gpu/drm/radeon/r100.c
parent85a331881dd52a93e7d4c57bcaf5486cc8718465 (diff)
drm/radeon/kms: avoid corner case issue with unmappable vram V2
We should not allocate any object into unmappable vram if we have no means to access them which on all GPU means having the CP running and on newer GPU having the blit utility working. This patch limit the vram allocation to visible vram until we have acceleration up and running. Note that it's more than unlikely that we run into any issue related to that as when acceleration is not woring userspace should allocate any object in vram beside front buffer which should fit in visible vram. V2 use real_vram_size as mc_vram_size could be bigger than the actual amount of vram [airlied: fixup r700_cp_stop case] Signed-off-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/r100.c')
-rw-r--r--drivers/gpu/drm/radeon/r100.c3
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c
index e151f16a8f86..e59422320bb6 100644
--- a/drivers/gpu/drm/radeon/r100.c
+++ b/drivers/gpu/drm/radeon/r100.c
@@ -1030,6 +1030,7 @@ int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
1030 return r; 1030 return r;
1031 } 1031 }
1032 rdev->cp.ready = true; 1032 rdev->cp.ready = true;
1033 rdev->mc.active_vram_size = rdev->mc.real_vram_size;
1033 return 0; 1034 return 0;
1034} 1035}
1035 1036
@@ -1047,6 +1048,7 @@ void r100_cp_fini(struct radeon_device *rdev)
1047void r100_cp_disable(struct radeon_device *rdev) 1048void r100_cp_disable(struct radeon_device *rdev)
1048{ 1049{
1049 /* Disable ring */ 1050 /* Disable ring */
1051 rdev->mc.active_vram_size = rdev->mc.visible_vram_size;
1050 rdev->cp.ready = false; 1052 rdev->cp.ready = false;
1051 WREG32(RADEON_CP_CSQ_MODE, 0); 1053 WREG32(RADEON_CP_CSQ_MODE, 0);
1052 WREG32(RADEON_CP_CSQ_CNTL, 0); 1054 WREG32(RADEON_CP_CSQ_CNTL, 0);
@@ -2295,6 +2297,7 @@ void r100_vram_init_sizes(struct radeon_device *rdev)
2295 /* FIXME we don't use the second aperture yet when we could use it */ 2297 /* FIXME we don't use the second aperture yet when we could use it */
2296 if (rdev->mc.visible_vram_size > rdev->mc.aper_size) 2298 if (rdev->mc.visible_vram_size > rdev->mc.aper_size)
2297 rdev->mc.visible_vram_size = rdev->mc.aper_size; 2299 rdev->mc.visible_vram_size = rdev->mc.aper_size;
2300 rdev->mc.active_vram_size = rdev->mc.visible_vram_size;
2298 config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE); 2301 config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
2299 if (rdev->flags & RADEON_IS_IGP) { 2302 if (rdev->flags & RADEON_IS_IGP) {
2300 uint32_t tom; 2303 uint32_t tom;