diff options
author | Christian Koenig <christian.koenig@amd.com> | 2012-05-17 13:52:00 -0400 |
---|---|---|
committer | Christian König <deathsimple@vodafone.de> | 2012-06-21 03:38:53 -0400 |
commit | 736fc37fd7c7634e939e9ec0c67765941913bb82 (patch) | |
tree | bf98094b72dc7b41ae4714a7b51f0e54d799419a /drivers/gpu/drm/radeon/r100.c | |
parent | fb98257a9d9d2089972b18079d5bdd4412e107e2 (diff) |
drm/radeon: replace pflip and sw_int counters with atomics
So we can skip the locking. Also renames sw_int to
ring_int, cause that better matches its purpose.
Signed-off-by: Christian Koenig <christian.koenig@amd.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/r100.c')
-rw-r--r-- | drivers/gpu/drm/radeon/r100.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c index e8fe4ae3bc23..35825bf1e790 100644 --- a/drivers/gpu/drm/radeon/r100.c +++ b/drivers/gpu/drm/radeon/r100.c | |||
@@ -689,18 +689,18 @@ int r100_irq_set(struct radeon_device *rdev) | |||
689 | WREG32(R_000040_GEN_INT_CNTL, 0); | 689 | WREG32(R_000040_GEN_INT_CNTL, 0); |
690 | return -EINVAL; | 690 | return -EINVAL; |
691 | } | 691 | } |
692 | if (rdev->irq.sw_int[RADEON_RING_TYPE_GFX_INDEX]) { | 692 | if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) { |
693 | tmp |= RADEON_SW_INT_ENABLE; | 693 | tmp |= RADEON_SW_INT_ENABLE; |
694 | } | 694 | } |
695 | if (rdev->irq.gui_idle) { | 695 | if (rdev->irq.gui_idle) { |
696 | tmp |= RADEON_GUI_IDLE_MASK; | 696 | tmp |= RADEON_GUI_IDLE_MASK; |
697 | } | 697 | } |
698 | if (rdev->irq.crtc_vblank_int[0] || | 698 | if (rdev->irq.crtc_vblank_int[0] || |
699 | rdev->irq.pflip[0]) { | 699 | atomic_read(&rdev->irq.pflip[0])) { |
700 | tmp |= RADEON_CRTC_VBLANK_MASK; | 700 | tmp |= RADEON_CRTC_VBLANK_MASK; |
701 | } | 701 | } |
702 | if (rdev->irq.crtc_vblank_int[1] || | 702 | if (rdev->irq.crtc_vblank_int[1] || |
703 | rdev->irq.pflip[1]) { | 703 | atomic_read(&rdev->irq.pflip[1])) { |
704 | tmp |= RADEON_CRTC2_VBLANK_MASK; | 704 | tmp |= RADEON_CRTC2_VBLANK_MASK; |
705 | } | 705 | } |
706 | if (rdev->irq.hpd[0]) { | 706 | if (rdev->irq.hpd[0]) { |
@@ -775,7 +775,7 @@ int r100_irq_process(struct radeon_device *rdev) | |||
775 | rdev->pm.vblank_sync = true; | 775 | rdev->pm.vblank_sync = true; |
776 | wake_up(&rdev->irq.vblank_queue); | 776 | wake_up(&rdev->irq.vblank_queue); |
777 | } | 777 | } |
778 | if (rdev->irq.pflip[0]) | 778 | if (atomic_read(&rdev->irq.pflip[0])) |
779 | radeon_crtc_handle_flip(rdev, 0); | 779 | radeon_crtc_handle_flip(rdev, 0); |
780 | } | 780 | } |
781 | if (status & RADEON_CRTC2_VBLANK_STAT) { | 781 | if (status & RADEON_CRTC2_VBLANK_STAT) { |
@@ -784,7 +784,7 @@ int r100_irq_process(struct radeon_device *rdev) | |||
784 | rdev->pm.vblank_sync = true; | 784 | rdev->pm.vblank_sync = true; |
785 | wake_up(&rdev->irq.vblank_queue); | 785 | wake_up(&rdev->irq.vblank_queue); |
786 | } | 786 | } |
787 | if (rdev->irq.pflip[1]) | 787 | if (atomic_read(&rdev->irq.pflip[1])) |
788 | radeon_crtc_handle_flip(rdev, 1); | 788 | radeon_crtc_handle_flip(rdev, 1); |
789 | } | 789 | } |
790 | if (status & RADEON_FP_DETECT_STAT) { | 790 | if (status & RADEON_FP_DETECT_STAT) { |