diff options
author | Ben Skeggs <bskeggs@redhat.com> | 2010-04-27 21:46:42 -0400 |
---|---|---|
committer | Dave Airlie <airlied@redhat.com> | 2010-05-18 04:21:33 -0400 |
commit | 68adac5e49436992e9c999fbae879d9ac5b72d4e (patch) | |
tree | 6593c74a8baf4a0424bbc5b2a06264c0a6a9338d /drivers/gpu/drm/radeon/r100.c | |
parent | 15a7df8db84e7a9d9915d879199ac4a870836c54 (diff) |
drm: move radeon_fixed.h to shared drm_fixed.h header
Will be used by nouveau driver also in the near future.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/r100.c')
-rw-r--r-- | drivers/gpu/drm/radeon/r100.c | 194 |
1 files changed, 97 insertions, 97 deletions
diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c index 87c4ffaf545e..a5f11c300f6a 100644 --- a/drivers/gpu/drm/radeon/r100.c +++ b/drivers/gpu/drm/radeon/r100.c | |||
@@ -2686,53 +2686,53 @@ void r100_bandwidth_update(struct radeon_device *rdev) | |||
2686 | fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff, crit_point_ff; | 2686 | fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff, crit_point_ff; |
2687 | uint32_t temp, data, mem_trcd, mem_trp, mem_tras; | 2687 | uint32_t temp, data, mem_trcd, mem_trp, mem_tras; |
2688 | fixed20_12 memtcas_ff[8] = { | 2688 | fixed20_12 memtcas_ff[8] = { |
2689 | fixed_init(1), | 2689 | dfixed_init(1), |
2690 | fixed_init(2), | 2690 | dfixed_init(2), |
2691 | fixed_init(3), | 2691 | dfixed_init(3), |
2692 | fixed_init(0), | 2692 | dfixed_init(0), |
2693 | fixed_init_half(1), | 2693 | dfixed_init_half(1), |
2694 | fixed_init_half(2), | 2694 | dfixed_init_half(2), |
2695 | fixed_init(0), | 2695 | dfixed_init(0), |
2696 | }; | 2696 | }; |
2697 | fixed20_12 memtcas_rs480_ff[8] = { | 2697 | fixed20_12 memtcas_rs480_ff[8] = { |
2698 | fixed_init(0), | 2698 | dfixed_init(0), |
2699 | fixed_init(1), | 2699 | dfixed_init(1), |
2700 | fixed_init(2), | 2700 | dfixed_init(2), |
2701 | fixed_init(3), | 2701 | dfixed_init(3), |
2702 | fixed_init(0), | 2702 | dfixed_init(0), |
2703 | fixed_init_half(1), | 2703 | dfixed_init_half(1), |
2704 | fixed_init_half(2), | 2704 | dfixed_init_half(2), |
2705 | fixed_init_half(3), | 2705 | dfixed_init_half(3), |
2706 | }; | 2706 | }; |
2707 | fixed20_12 memtcas2_ff[8] = { | 2707 | fixed20_12 memtcas2_ff[8] = { |
2708 | fixed_init(0), | 2708 | dfixed_init(0), |
2709 | fixed_init(1), | 2709 | dfixed_init(1), |
2710 | fixed_init(2), | 2710 | dfixed_init(2), |
2711 | fixed_init(3), | 2711 | dfixed_init(3), |
2712 | fixed_init(4), | 2712 | dfixed_init(4), |
2713 | fixed_init(5), | 2713 | dfixed_init(5), |
2714 | fixed_init(6), | 2714 | dfixed_init(6), |
2715 | fixed_init(7), | 2715 | dfixed_init(7), |
2716 | }; | 2716 | }; |
2717 | fixed20_12 memtrbs[8] = { | 2717 | fixed20_12 memtrbs[8] = { |
2718 | fixed_init(1), | 2718 | dfixed_init(1), |
2719 | fixed_init_half(1), | 2719 | dfixed_init_half(1), |
2720 | fixed_init(2), | 2720 | dfixed_init(2), |
2721 | fixed_init_half(2), | 2721 | dfixed_init_half(2), |
2722 | fixed_init(3), | 2722 | dfixed_init(3), |
2723 | fixed_init_half(3), | 2723 | dfixed_init_half(3), |
2724 | fixed_init(4), | 2724 | dfixed_init(4), |
2725 | fixed_init_half(4) | 2725 | dfixed_init_half(4) |
2726 | }; | 2726 | }; |
2727 | fixed20_12 memtrbs_r4xx[8] = { | 2727 | fixed20_12 memtrbs_r4xx[8] = { |
2728 | fixed_init(4), | 2728 | dfixed_init(4), |
2729 | fixed_init(5), | 2729 | dfixed_init(5), |
2730 | fixed_init(6), | 2730 | dfixed_init(6), |
2731 | fixed_init(7), | 2731 | dfixed_init(7), |
2732 | fixed_init(8), | 2732 | dfixed_init(8), |
2733 | fixed_init(9), | 2733 | dfixed_init(9), |
2734 | fixed_init(10), | 2734 | dfixed_init(10), |
2735 | fixed_init(11) | 2735 | dfixed_init(11) |
2736 | }; | 2736 | }; |
2737 | fixed20_12 min_mem_eff; | 2737 | fixed20_12 min_mem_eff; |
2738 | fixed20_12 mc_latency_sclk, mc_latency_mclk, k1; | 2738 | fixed20_12 mc_latency_sclk, mc_latency_mclk, k1; |
@@ -2763,7 +2763,7 @@ void r100_bandwidth_update(struct radeon_device *rdev) | |||
2763 | } | 2763 | } |
2764 | } | 2764 | } |
2765 | 2765 | ||
2766 | min_mem_eff.full = rfixed_const_8(0); | 2766 | min_mem_eff.full = dfixed_const_8(0); |
2767 | /* get modes */ | 2767 | /* get modes */ |
2768 | if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) { | 2768 | if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) { |
2769 | uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER); | 2769 | uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER); |
@@ -2784,28 +2784,28 @@ void r100_bandwidth_update(struct radeon_device *rdev) | |||
2784 | mclk_ff = rdev->pm.mclk; | 2784 | mclk_ff = rdev->pm.mclk; |
2785 | 2785 | ||
2786 | temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1); | 2786 | temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1); |
2787 | temp_ff.full = rfixed_const(temp); | 2787 | temp_ff.full = dfixed_const(temp); |
2788 | mem_bw.full = rfixed_mul(mclk_ff, temp_ff); | 2788 | mem_bw.full = dfixed_mul(mclk_ff, temp_ff); |
2789 | 2789 | ||
2790 | pix_clk.full = 0; | 2790 | pix_clk.full = 0; |
2791 | pix_clk2.full = 0; | 2791 | pix_clk2.full = 0; |
2792 | peak_disp_bw.full = 0; | 2792 | peak_disp_bw.full = 0; |
2793 | if (mode1) { | 2793 | if (mode1) { |
2794 | temp_ff.full = rfixed_const(1000); | 2794 | temp_ff.full = dfixed_const(1000); |
2795 | pix_clk.full = rfixed_const(mode1->clock); /* convert to fixed point */ | 2795 | pix_clk.full = dfixed_const(mode1->clock); /* convert to fixed point */ |
2796 | pix_clk.full = rfixed_div(pix_clk, temp_ff); | 2796 | pix_clk.full = dfixed_div(pix_clk, temp_ff); |
2797 | temp_ff.full = rfixed_const(pixel_bytes1); | 2797 | temp_ff.full = dfixed_const(pixel_bytes1); |
2798 | peak_disp_bw.full += rfixed_mul(pix_clk, temp_ff); | 2798 | peak_disp_bw.full += dfixed_mul(pix_clk, temp_ff); |
2799 | } | 2799 | } |
2800 | if (mode2) { | 2800 | if (mode2) { |
2801 | temp_ff.full = rfixed_const(1000); | 2801 | temp_ff.full = dfixed_const(1000); |
2802 | pix_clk2.full = rfixed_const(mode2->clock); /* convert to fixed point */ | 2802 | pix_clk2.full = dfixed_const(mode2->clock); /* convert to fixed point */ |
2803 | pix_clk2.full = rfixed_div(pix_clk2, temp_ff); | 2803 | pix_clk2.full = dfixed_div(pix_clk2, temp_ff); |
2804 | temp_ff.full = rfixed_const(pixel_bytes2); | 2804 | temp_ff.full = dfixed_const(pixel_bytes2); |
2805 | peak_disp_bw.full += rfixed_mul(pix_clk2, temp_ff); | 2805 | peak_disp_bw.full += dfixed_mul(pix_clk2, temp_ff); |
2806 | } | 2806 | } |
2807 | 2807 | ||
2808 | mem_bw.full = rfixed_mul(mem_bw, min_mem_eff); | 2808 | mem_bw.full = dfixed_mul(mem_bw, min_mem_eff); |
2809 | if (peak_disp_bw.full >= mem_bw.full) { | 2809 | if (peak_disp_bw.full >= mem_bw.full) { |
2810 | DRM_ERROR("You may not have enough display bandwidth for current mode\n" | 2810 | DRM_ERROR("You may not have enough display bandwidth for current mode\n" |
2811 | "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n"); | 2811 | "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n"); |
@@ -2847,9 +2847,9 @@ void r100_bandwidth_update(struct radeon_device *rdev) | |||
2847 | mem_tras = ((temp >> 12) & 0xf) + 4; | 2847 | mem_tras = ((temp >> 12) & 0xf) + 4; |
2848 | } | 2848 | } |
2849 | /* convert to FF */ | 2849 | /* convert to FF */ |
2850 | trcd_ff.full = rfixed_const(mem_trcd); | 2850 | trcd_ff.full = dfixed_const(mem_trcd); |
2851 | trp_ff.full = rfixed_const(mem_trp); | 2851 | trp_ff.full = dfixed_const(mem_trp); |
2852 | tras_ff.full = rfixed_const(mem_tras); | 2852 | tras_ff.full = dfixed_const(mem_tras); |
2853 | 2853 | ||
2854 | /* Get values from the MEM_SDRAM_MODE_REG register...converting its */ | 2854 | /* Get values from the MEM_SDRAM_MODE_REG register...converting its */ |
2855 | temp = RREG32(RADEON_MEM_SDRAM_MODE_REG); | 2855 | temp = RREG32(RADEON_MEM_SDRAM_MODE_REG); |
@@ -2867,7 +2867,7 @@ void r100_bandwidth_update(struct radeon_device *rdev) | |||
2867 | /* extra cas latency stored in bits 23-25 0-4 clocks */ | 2867 | /* extra cas latency stored in bits 23-25 0-4 clocks */ |
2868 | data = (temp >> 23) & 0x7; | 2868 | data = (temp >> 23) & 0x7; |
2869 | if (data < 5) | 2869 | if (data < 5) |
2870 | tcas_ff.full += rfixed_const(data); | 2870 | tcas_ff.full += dfixed_const(data); |
2871 | } | 2871 | } |
2872 | 2872 | ||
2873 | if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) { | 2873 | if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) { |
@@ -2904,72 +2904,72 @@ void r100_bandwidth_update(struct radeon_device *rdev) | |||
2904 | 2904 | ||
2905 | if (rdev->flags & RADEON_IS_AGP) { | 2905 | if (rdev->flags & RADEON_IS_AGP) { |
2906 | fixed20_12 agpmode_ff; | 2906 | fixed20_12 agpmode_ff; |
2907 | agpmode_ff.full = rfixed_const(radeon_agpmode); | 2907 | agpmode_ff.full = dfixed_const(radeon_agpmode); |
2908 | temp_ff.full = rfixed_const_666(16); | 2908 | temp_ff.full = dfixed_const_666(16); |
2909 | sclk_eff_ff.full -= rfixed_mul(agpmode_ff, temp_ff); | 2909 | sclk_eff_ff.full -= dfixed_mul(agpmode_ff, temp_ff); |
2910 | } | 2910 | } |
2911 | /* TODO PCIE lanes may affect this - agpmode == 16?? */ | 2911 | /* TODO PCIE lanes may affect this - agpmode == 16?? */ |
2912 | 2912 | ||
2913 | if (ASIC_IS_R300(rdev)) { | 2913 | if (ASIC_IS_R300(rdev)) { |
2914 | sclk_delay_ff.full = rfixed_const(250); | 2914 | sclk_delay_ff.full = dfixed_const(250); |
2915 | } else { | 2915 | } else { |
2916 | if ((rdev->family == CHIP_RV100) || | 2916 | if ((rdev->family == CHIP_RV100) || |
2917 | rdev->flags & RADEON_IS_IGP) { | 2917 | rdev->flags & RADEON_IS_IGP) { |
2918 | if (rdev->mc.vram_is_ddr) | 2918 | if (rdev->mc.vram_is_ddr) |
2919 | sclk_delay_ff.full = rfixed_const(41); | 2919 | sclk_delay_ff.full = dfixed_const(41); |
2920 | else | 2920 | else |
2921 | sclk_delay_ff.full = rfixed_const(33); | 2921 | sclk_delay_ff.full = dfixed_const(33); |
2922 | } else { | 2922 | } else { |
2923 | if (rdev->mc.vram_width == 128) | 2923 | if (rdev->mc.vram_width == 128) |
2924 | sclk_delay_ff.full = rfixed_const(57); | 2924 | sclk_delay_ff.full = dfixed_const(57); |
2925 | else | 2925 | else |
2926 | sclk_delay_ff.full = rfixed_const(41); | 2926 | sclk_delay_ff.full = dfixed_const(41); |
2927 | } | 2927 | } |
2928 | } | 2928 | } |
2929 | 2929 | ||
2930 | mc_latency_sclk.full = rfixed_div(sclk_delay_ff, sclk_eff_ff); | 2930 | mc_latency_sclk.full = dfixed_div(sclk_delay_ff, sclk_eff_ff); |
2931 | 2931 | ||
2932 | if (rdev->mc.vram_is_ddr) { | 2932 | if (rdev->mc.vram_is_ddr) { |
2933 | if (rdev->mc.vram_width == 32) { | 2933 | if (rdev->mc.vram_width == 32) { |
2934 | k1.full = rfixed_const(40); | 2934 | k1.full = dfixed_const(40); |
2935 | c = 3; | 2935 | c = 3; |
2936 | } else { | 2936 | } else { |
2937 | k1.full = rfixed_const(20); | 2937 | k1.full = dfixed_const(20); |
2938 | c = 1; | 2938 | c = 1; |
2939 | } | 2939 | } |
2940 | } else { | 2940 | } else { |
2941 | k1.full = rfixed_const(40); | 2941 | k1.full = dfixed_const(40); |
2942 | c = 3; | 2942 | c = 3; |
2943 | } | 2943 | } |
2944 | 2944 | ||
2945 | temp_ff.full = rfixed_const(2); | 2945 | temp_ff.full = dfixed_const(2); |
2946 | mc_latency_mclk.full = rfixed_mul(trcd_ff, temp_ff); | 2946 | mc_latency_mclk.full = dfixed_mul(trcd_ff, temp_ff); |
2947 | temp_ff.full = rfixed_const(c); | 2947 | temp_ff.full = dfixed_const(c); |
2948 | mc_latency_mclk.full += rfixed_mul(tcas_ff, temp_ff); | 2948 | mc_latency_mclk.full += dfixed_mul(tcas_ff, temp_ff); |
2949 | temp_ff.full = rfixed_const(4); | 2949 | temp_ff.full = dfixed_const(4); |
2950 | mc_latency_mclk.full += rfixed_mul(tras_ff, temp_ff); | 2950 | mc_latency_mclk.full += dfixed_mul(tras_ff, temp_ff); |
2951 | mc_latency_mclk.full += rfixed_mul(trp_ff, temp_ff); | 2951 | mc_latency_mclk.full += dfixed_mul(trp_ff, temp_ff); |
2952 | mc_latency_mclk.full += k1.full; | 2952 | mc_latency_mclk.full += k1.full; |
2953 | 2953 | ||
2954 | mc_latency_mclk.full = rfixed_div(mc_latency_mclk, mclk_ff); | 2954 | mc_latency_mclk.full = dfixed_div(mc_latency_mclk, mclk_ff); |
2955 | mc_latency_mclk.full += rfixed_div(temp_ff, sclk_eff_ff); | 2955 | mc_latency_mclk.full += dfixed_div(temp_ff, sclk_eff_ff); |
2956 | 2956 | ||
2957 | /* | 2957 | /* |
2958 | HW cursor time assuming worst case of full size colour cursor. | 2958 | HW cursor time assuming worst case of full size colour cursor. |
2959 | */ | 2959 | */ |
2960 | temp_ff.full = rfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1)))); | 2960 | temp_ff.full = dfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1)))); |
2961 | temp_ff.full += trcd_ff.full; | 2961 | temp_ff.full += trcd_ff.full; |
2962 | if (temp_ff.full < tras_ff.full) | 2962 | if (temp_ff.full < tras_ff.full) |
2963 | temp_ff.full = tras_ff.full; | 2963 | temp_ff.full = tras_ff.full; |
2964 | cur_latency_mclk.full = rfixed_div(temp_ff, mclk_ff); | 2964 | cur_latency_mclk.full = dfixed_div(temp_ff, mclk_ff); |
2965 | 2965 | ||
2966 | temp_ff.full = rfixed_const(cur_size); | 2966 | temp_ff.full = dfixed_const(cur_size); |
2967 | cur_latency_sclk.full = rfixed_div(temp_ff, sclk_eff_ff); | 2967 | cur_latency_sclk.full = dfixed_div(temp_ff, sclk_eff_ff); |
2968 | /* | 2968 | /* |
2969 | Find the total latency for the display data. | 2969 | Find the total latency for the display data. |
2970 | */ | 2970 | */ |
2971 | disp_latency_overhead.full = rfixed_const(8); | 2971 | disp_latency_overhead.full = dfixed_const(8); |
2972 | disp_latency_overhead.full = rfixed_div(disp_latency_overhead, sclk_ff); | 2972 | disp_latency_overhead.full = dfixed_div(disp_latency_overhead, sclk_ff); |
2973 | mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full; | 2973 | mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full; |
2974 | mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full; | 2974 | mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full; |
2975 | 2975 | ||
@@ -2997,16 +2997,16 @@ void r100_bandwidth_update(struct radeon_device *rdev) | |||
2997 | /* | 2997 | /* |
2998 | Find the drain rate of the display buffer. | 2998 | Find the drain rate of the display buffer. |
2999 | */ | 2999 | */ |
3000 | temp_ff.full = rfixed_const((16/pixel_bytes1)); | 3000 | temp_ff.full = dfixed_const((16/pixel_bytes1)); |
3001 | disp_drain_rate.full = rfixed_div(pix_clk, temp_ff); | 3001 | disp_drain_rate.full = dfixed_div(pix_clk, temp_ff); |
3002 | 3002 | ||
3003 | /* | 3003 | /* |
3004 | Find the critical point of the display buffer. | 3004 | Find the critical point of the display buffer. |
3005 | */ | 3005 | */ |
3006 | crit_point_ff.full = rfixed_mul(disp_drain_rate, disp_latency); | 3006 | crit_point_ff.full = dfixed_mul(disp_drain_rate, disp_latency); |
3007 | crit_point_ff.full += rfixed_const_half(0); | 3007 | crit_point_ff.full += dfixed_const_half(0); |
3008 | 3008 | ||
3009 | critical_point = rfixed_trunc(crit_point_ff); | 3009 | critical_point = dfixed_trunc(crit_point_ff); |
3010 | 3010 | ||
3011 | if (rdev->disp_priority == 2) { | 3011 | if (rdev->disp_priority == 2) { |
3012 | critical_point = 0; | 3012 | critical_point = 0; |
@@ -3077,8 +3077,8 @@ void r100_bandwidth_update(struct radeon_device *rdev) | |||
3077 | /* | 3077 | /* |
3078 | Find the drain rate of the display buffer. | 3078 | Find the drain rate of the display buffer. |
3079 | */ | 3079 | */ |
3080 | temp_ff.full = rfixed_const((16/pixel_bytes2)); | 3080 | temp_ff.full = dfixed_const((16/pixel_bytes2)); |
3081 | disp_drain_rate2.full = rfixed_div(pix_clk2, temp_ff); | 3081 | disp_drain_rate2.full = dfixed_div(pix_clk2, temp_ff); |
3082 | 3082 | ||
3083 | grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL); | 3083 | grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL); |
3084 | grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK); | 3084 | grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK); |
@@ -3099,8 +3099,8 @@ void r100_bandwidth_update(struct radeon_device *rdev) | |||
3099 | critical_point2 = 0; | 3099 | critical_point2 = 0; |
3100 | else { | 3100 | else { |
3101 | temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128; | 3101 | temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128; |
3102 | temp_ff.full = rfixed_const(temp); | 3102 | temp_ff.full = dfixed_const(temp); |
3103 | temp_ff.full = rfixed_mul(mclk_ff, temp_ff); | 3103 | temp_ff.full = dfixed_mul(mclk_ff, temp_ff); |
3104 | if (sclk_ff.full < temp_ff.full) | 3104 | if (sclk_ff.full < temp_ff.full) |
3105 | temp_ff.full = sclk_ff.full; | 3105 | temp_ff.full = sclk_ff.full; |
3106 | 3106 | ||
@@ -3108,15 +3108,15 @@ void r100_bandwidth_update(struct radeon_device *rdev) | |||
3108 | 3108 | ||
3109 | if (mode1) { | 3109 | if (mode1) { |
3110 | temp_ff.full = read_return_rate.full - disp_drain_rate.full; | 3110 | temp_ff.full = read_return_rate.full - disp_drain_rate.full; |
3111 | time_disp1_drop_priority.full = rfixed_div(crit_point_ff, temp_ff); | 3111 | time_disp1_drop_priority.full = dfixed_div(crit_point_ff, temp_ff); |
3112 | } else { | 3112 | } else { |
3113 | time_disp1_drop_priority.full = 0; | 3113 | time_disp1_drop_priority.full = 0; |
3114 | } | 3114 | } |
3115 | crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full; | 3115 | crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full; |
3116 | crit_point_ff.full = rfixed_mul(crit_point_ff, disp_drain_rate2); | 3116 | crit_point_ff.full = dfixed_mul(crit_point_ff, disp_drain_rate2); |
3117 | crit_point_ff.full += rfixed_const_half(0); | 3117 | crit_point_ff.full += dfixed_const_half(0); |
3118 | 3118 | ||
3119 | critical_point2 = rfixed_trunc(crit_point_ff); | 3119 | critical_point2 = dfixed_trunc(crit_point_ff); |
3120 | 3120 | ||
3121 | if (rdev->disp_priority == 2) { | 3121 | if (rdev->disp_priority == 2) { |
3122 | critical_point2 = 0; | 3122 | critical_point2 = 0; |