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authorAlex Deucher <alexander.deucher@amd.com>2013-03-11 19:28:39 -0400
committerAlex Deucher <alexander.deucher@amd.com>2013-03-15 18:47:17 -0400
commit8f612b23a17dce86fef75407e698de6243cc99a1 (patch)
treede94464a0baae97de4d142324d990f8f4f5424ea /drivers/gpu/drm/radeon/ni.c
parentfa3daf9aa74a3ac1c87d8188a43d283d06720032 (diff)
drm/radeon: fix backend map setup on 1 RB trinity boards
Need to adjust the backend map depending on which RB is enabled. This is the trinity equivalent of: f7eb97300832f4fe5fe916c5d84cd2e25169330e May fix: https://bugs.freedesktop.org/show_bug.cgi?id=57919 Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
Diffstat (limited to 'drivers/gpu/drm/radeon/ni.c')
-rw-r--r--drivers/gpu/drm/radeon/ni.c21
1 files changed, 16 insertions, 5 deletions
diff --git a/drivers/gpu/drm/radeon/ni.c b/drivers/gpu/drm/radeon/ni.c
index e77c9273bc9c..a7d3de73be04 100644
--- a/drivers/gpu/drm/radeon/ni.c
+++ b/drivers/gpu/drm/radeon/ni.c
@@ -616,11 +616,22 @@ static void cayman_gpu_init(struct radeon_device *rdev)
616 WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config); 616 WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config);
617 WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config); 617 WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config);
618 618
619 tmp = gb_addr_config & NUM_PIPES_MASK; 619 if ((rdev->config.cayman.max_backends_per_se == 1) &&
620 tmp = r6xx_remap_render_backend(rdev, tmp, 620 (rdev->flags & RADEON_IS_IGP)) {
621 rdev->config.cayman.max_backends_per_se * 621 if ((disabled_rb_mask & 3) == 1) {
622 rdev->config.cayman.max_shader_engines, 622 /* RB0 disabled, RB1 enabled */
623 CAYMAN_MAX_BACKENDS, disabled_rb_mask); 623 tmp = 0x11111111;
624 } else {
625 /* RB1 disabled, RB0 enabled */
626 tmp = 0x00000000;
627 }
628 } else {
629 tmp = gb_addr_config & NUM_PIPES_MASK;
630 tmp = r6xx_remap_render_backend(rdev, tmp,
631 rdev->config.cayman.max_backends_per_se *
632 rdev->config.cayman.max_shader_engines,
633 CAYMAN_MAX_BACKENDS, disabled_rb_mask);
634 }
624 WREG32(GB_BACKEND_MAP, tmp); 635 WREG32(GB_BACKEND_MAP, tmp);
625 636
626 cgts_tcc_disable = 0xffff0000; 637 cgts_tcc_disable = 0xffff0000;