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authorAlex Deucher <alexdeucher@gmail.com>2011-03-02 20:07:29 -0500
committerDave Airlie <airlied@redhat.com>2011-03-02 20:50:59 -0500
commitfecf1d072f96114266ed3aae8c4fb93f9c179b00 (patch)
tree82d312f3dc9019f03bcdbd84df9d242cdd811b54 /drivers/gpu/drm/radeon/ni.c
parent9b8253ce204ad9fcd2aec315066492dfbc73e409 (diff)
drm/radeon/kms: add gpu_init function for cayman
This may some work to get accel going. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/ni.c')
-rw-r--r--drivers/gpu/drm/radeon/ni.c550
1 files changed, 550 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/ni.c b/drivers/gpu/drm/radeon/ni.c
index 058aa4f84d19..eaefb5b066db 100644
--- a/drivers/gpu/drm/radeon/ni.c
+++ b/drivers/gpu/drm/radeon/ni.c
@@ -381,3 +381,553 @@ out:
381 return err; 381 return err;
382} 382}
383 383
384/*
385 * Core functions
386 */
387static u32 cayman_get_tile_pipe_to_backend_map(struct radeon_device *rdev,
388 u32 num_tile_pipes,
389 u32 num_backends_per_asic,
390 u32 *backend_disable_mask_per_asic,
391 u32 num_shader_engines)
392{
393 u32 backend_map = 0;
394 u32 enabled_backends_mask = 0;
395 u32 enabled_backends_count = 0;
396 u32 num_backends_per_se;
397 u32 cur_pipe;
398 u32 swizzle_pipe[CAYMAN_MAX_PIPES];
399 u32 cur_backend = 0;
400 u32 i;
401 bool force_no_swizzle;
402
403 /* force legal values */
404 if (num_tile_pipes < 1)
405 num_tile_pipes = 1;
406 if (num_tile_pipes > rdev->config.cayman.max_tile_pipes)
407 num_tile_pipes = rdev->config.cayman.max_tile_pipes;
408 if (num_shader_engines < 1)
409 num_shader_engines = 1;
410 if (num_shader_engines > rdev->config.cayman.max_shader_engines)
411 num_shader_engines = rdev->config.cayman.max_shader_engines;
412 if (num_backends_per_asic > num_shader_engines)
413 num_backends_per_asic = num_shader_engines;
414 if (num_backends_per_asic > (rdev->config.cayman.max_backends_per_se * num_shader_engines))
415 num_backends_per_asic = rdev->config.cayman.max_backends_per_se * num_shader_engines;
416
417 /* make sure we have the same number of backends per se */
418 num_backends_per_asic = ALIGN(num_backends_per_asic, num_shader_engines);
419 /* set up the number of backends per se */
420 num_backends_per_se = num_backends_per_asic / num_shader_engines;
421 if (num_backends_per_se > rdev->config.cayman.max_backends_per_se) {
422 num_backends_per_se = rdev->config.cayman.max_backends_per_se;
423 num_backends_per_asic = num_backends_per_se * num_shader_engines;
424 }
425
426 /* create enable mask and count for enabled backends */
427 for (i = 0; i < CAYMAN_MAX_BACKENDS; ++i) {
428 if (((*backend_disable_mask_per_asic >> i) & 1) == 0) {
429 enabled_backends_mask |= (1 << i);
430 ++enabled_backends_count;
431 }
432 if (enabled_backends_count == num_backends_per_asic)
433 break;
434 }
435
436 /* force the backends mask to match the current number of backends */
437 if (enabled_backends_count != num_backends_per_asic) {
438 u32 this_backend_enabled;
439 u32 shader_engine;
440 u32 backend_per_se;
441
442 enabled_backends_mask = 0;
443 enabled_backends_count = 0;
444 *backend_disable_mask_per_asic = CAYMAN_MAX_BACKENDS_MASK;
445 for (i = 0; i < CAYMAN_MAX_BACKENDS; ++i) {
446 /* calc the current se */
447 shader_engine = i / rdev->config.cayman.max_backends_per_se;
448 /* calc the backend per se */
449 backend_per_se = i % rdev->config.cayman.max_backends_per_se;
450 /* default to not enabled */
451 this_backend_enabled = 0;
452 if ((shader_engine < num_shader_engines) &&
453 (backend_per_se < num_backends_per_se))
454 this_backend_enabled = 1;
455 if (this_backend_enabled) {
456 enabled_backends_mask |= (1 << i);
457 *backend_disable_mask_per_asic &= ~(1 << i);
458 ++enabled_backends_count;
459 }
460 }
461 }
462
463
464 memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * CAYMAN_MAX_PIPES);
465 switch (rdev->family) {
466 case CHIP_CAYMAN:
467 force_no_swizzle = true;
468 break;
469 default:
470 force_no_swizzle = false;
471 break;
472 }
473 if (force_no_swizzle) {
474 bool last_backend_enabled = false;
475
476 force_no_swizzle = false;
477 for (i = 0; i < CAYMAN_MAX_BACKENDS; ++i) {
478 if (((enabled_backends_mask >> i) & 1) == 1) {
479 if (last_backend_enabled)
480 force_no_swizzle = true;
481 last_backend_enabled = true;
482 } else
483 last_backend_enabled = false;
484 }
485 }
486
487 switch (num_tile_pipes) {
488 case 1:
489 case 3:
490 case 5:
491 case 7:
492 DRM_ERROR("odd number of pipes!\n");
493 break;
494 case 2:
495 swizzle_pipe[0] = 0;
496 swizzle_pipe[1] = 1;
497 break;
498 case 4:
499 if (force_no_swizzle) {
500 swizzle_pipe[0] = 0;
501 swizzle_pipe[1] = 1;
502 swizzle_pipe[2] = 2;
503 swizzle_pipe[3] = 3;
504 } else {
505 swizzle_pipe[0] = 0;
506 swizzle_pipe[1] = 2;
507 swizzle_pipe[2] = 1;
508 swizzle_pipe[3] = 3;
509 }
510 break;
511 case 6:
512 if (force_no_swizzle) {
513 swizzle_pipe[0] = 0;
514 swizzle_pipe[1] = 1;
515 swizzle_pipe[2] = 2;
516 swizzle_pipe[3] = 3;
517 swizzle_pipe[4] = 4;
518 swizzle_pipe[5] = 5;
519 } else {
520 swizzle_pipe[0] = 0;
521 swizzle_pipe[1] = 2;
522 swizzle_pipe[2] = 4;
523 swizzle_pipe[3] = 1;
524 swizzle_pipe[4] = 3;
525 swizzle_pipe[5] = 5;
526 }
527 break;
528 case 8:
529 if (force_no_swizzle) {
530 swizzle_pipe[0] = 0;
531 swizzle_pipe[1] = 1;
532 swizzle_pipe[2] = 2;
533 swizzle_pipe[3] = 3;
534 swizzle_pipe[4] = 4;
535 swizzle_pipe[5] = 5;
536 swizzle_pipe[6] = 6;
537 swizzle_pipe[7] = 7;
538 } else {
539 swizzle_pipe[0] = 0;
540 swizzle_pipe[1] = 2;
541 swizzle_pipe[2] = 4;
542 swizzle_pipe[3] = 6;
543 swizzle_pipe[4] = 1;
544 swizzle_pipe[5] = 3;
545 swizzle_pipe[6] = 5;
546 swizzle_pipe[7] = 7;
547 }
548 break;
549 }
550
551 for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
552 while (((1 << cur_backend) & enabled_backends_mask) == 0)
553 cur_backend = (cur_backend + 1) % CAYMAN_MAX_BACKENDS;
554
555 backend_map |= (((cur_backend & 0xf) << (swizzle_pipe[cur_pipe] * 4)));
556
557 cur_backend = (cur_backend + 1) % CAYMAN_MAX_BACKENDS;
558 }
559
560 return backend_map;
561}
562
563static void cayman_program_channel_remap(struct radeon_device *rdev)
564{
565 u32 tcp_chan_steer_lo, tcp_chan_steer_hi, mc_shared_chremap, tmp;
566
567 tmp = RREG32(MC_SHARED_CHMAP);
568 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
569 case 0:
570 case 1:
571 case 2:
572 case 3:
573 default:
574 /* default mapping */
575 mc_shared_chremap = 0x00fac688;
576 break;
577 }
578
579 switch (rdev->family) {
580 case CHIP_CAYMAN:
581 default:
582 //tcp_chan_steer_lo = 0x54763210
583 tcp_chan_steer_lo = 0x76543210;
584 tcp_chan_steer_hi = 0x0000ba98;
585 break;
586 }
587
588 WREG32(TCP_CHAN_STEER_LO, tcp_chan_steer_lo);
589 WREG32(TCP_CHAN_STEER_HI, tcp_chan_steer_hi);
590 WREG32(MC_SHARED_CHREMAP, mc_shared_chremap);
591}
592
593static u32 cayman_get_disable_mask_per_asic(struct radeon_device *rdev,
594 u32 disable_mask_per_se,
595 u32 max_disable_mask_per_se,
596 u32 num_shader_engines)
597{
598 u32 disable_field_width_per_se = r600_count_pipe_bits(disable_mask_per_se);
599 u32 disable_mask_per_asic = disable_mask_per_se & max_disable_mask_per_se;
600
601 if (num_shader_engines == 1)
602 return disable_mask_per_asic;
603 else if (num_shader_engines == 2)
604 return disable_mask_per_asic | (disable_mask_per_asic << disable_field_width_per_se);
605 else
606 return 0xffffffff;
607}
608
609static void cayman_gpu_init(struct radeon_device *rdev)
610{
611 u32 cc_rb_backend_disable = 0;
612 u32 cc_gc_shader_pipe_config;
613 u32 gb_addr_config = 0;
614 u32 mc_shared_chmap, mc_arb_ramcfg;
615 u32 gb_backend_map;
616 u32 cgts_tcc_disable;
617 u32 sx_debug_1;
618 u32 smx_dc_ctl0;
619 u32 gc_user_shader_pipe_config;
620 u32 gc_user_rb_backend_disable;
621 u32 cgts_user_tcc_disable;
622 u32 cgts_sm_ctrl_reg;
623 u32 hdp_host_path_cntl;
624 u32 tmp;
625 int i, j;
626
627 switch (rdev->family) {
628 case CHIP_CAYMAN:
629 default:
630 rdev->config.cayman.max_shader_engines = 2;
631 rdev->config.cayman.max_pipes_per_simd = 4;
632 rdev->config.cayman.max_tile_pipes = 8;
633 rdev->config.cayman.max_simds_per_se = 12;
634 rdev->config.cayman.max_backends_per_se = 4;
635 rdev->config.cayman.max_texture_channel_caches = 8;
636 rdev->config.cayman.max_gprs = 256;
637 rdev->config.cayman.max_threads = 256;
638 rdev->config.cayman.max_gs_threads = 32;
639 rdev->config.cayman.max_stack_entries = 512;
640 rdev->config.cayman.sx_num_of_sets = 8;
641 rdev->config.cayman.sx_max_export_size = 256;
642 rdev->config.cayman.sx_max_export_pos_size = 64;
643 rdev->config.cayman.sx_max_export_smx_size = 192;
644 rdev->config.cayman.max_hw_contexts = 8;
645 rdev->config.cayman.sq_num_cf_insts = 2;
646
647 rdev->config.cayman.sc_prim_fifo_size = 0x100;
648 rdev->config.cayman.sc_hiz_tile_fifo_size = 0x30;
649 rdev->config.cayman.sc_earlyz_tile_fifo_size = 0x130;
650 break;
651 }
652
653 /* Initialize HDP */
654 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
655 WREG32((0x2c14 + j), 0x00000000);
656 WREG32((0x2c18 + j), 0x00000000);
657 WREG32((0x2c1c + j), 0x00000000);
658 WREG32((0x2c20 + j), 0x00000000);
659 WREG32((0x2c24 + j), 0x00000000);
660 }
661
662 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
663
664 mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
665 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
666
667 cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE);
668 cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG);
669 cgts_tcc_disable = RREG32(CGTS_TCC_DISABLE);
670 gc_user_rb_backend_disable = RREG32(GC_USER_RB_BACKEND_DISABLE);
671 gc_user_shader_pipe_config = RREG32(GC_USER_SHADER_PIPE_CONFIG);
672 cgts_user_tcc_disable = RREG32(CGTS_USER_TCC_DISABLE);
673
674 rdev->config.cayman.num_shader_engines = rdev->config.cayman.max_shader_engines;
675 tmp = ((~gc_user_shader_pipe_config) & INACTIVE_QD_PIPES_MASK) >> INACTIVE_QD_PIPES_SHIFT;
676 rdev->config.cayman.num_shader_pipes_per_simd = r600_count_pipe_bits(tmp);
677 rdev->config.cayman.num_tile_pipes = rdev->config.cayman.max_tile_pipes;
678 tmp = ((~gc_user_shader_pipe_config) & INACTIVE_SIMDS_MASK) >> INACTIVE_SIMDS_SHIFT;
679 rdev->config.cayman.num_simds_per_se = r600_count_pipe_bits(tmp);
680 tmp = ((~gc_user_rb_backend_disable) & BACKEND_DISABLE_MASK) >> BACKEND_DISABLE_SHIFT;
681 rdev->config.cayman.num_backends_per_se = r600_count_pipe_bits(tmp);
682 tmp = (gc_user_rb_backend_disable & BACKEND_DISABLE_MASK) >> BACKEND_DISABLE_SHIFT;
683 rdev->config.cayman.backend_disable_mask_per_asic =
684 cayman_get_disable_mask_per_asic(rdev, tmp, CAYMAN_MAX_BACKENDS_PER_SE_MASK,
685 rdev->config.cayman.num_shader_engines);
686 rdev->config.cayman.backend_map =
687 cayman_get_tile_pipe_to_backend_map(rdev, rdev->config.cayman.num_tile_pipes,
688 rdev->config.cayman.num_backends_per_se *
689 rdev->config.cayman.num_shader_engines,
690 &rdev->config.cayman.backend_disable_mask_per_asic,
691 rdev->config.cayman.num_shader_engines);
692 tmp = ((~cgts_user_tcc_disable) & TCC_DISABLE_MASK) >> TCC_DISABLE_SHIFT;
693 rdev->config.cayman.num_texture_channel_caches = r600_count_pipe_bits(tmp);
694 tmp = (mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT;
695 rdev->config.cayman.mem_max_burst_length_bytes = (tmp + 1) * 256;
696 if (rdev->config.cayman.mem_max_burst_length_bytes > 512)
697 rdev->config.cayman.mem_max_burst_length_bytes = 512;
698 tmp = (mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT;
699 rdev->config.cayman.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
700 if (rdev->config.cayman.mem_row_size_in_kb > 4)
701 rdev->config.cayman.mem_row_size_in_kb = 4;
702 /* XXX use MC settings? */
703 rdev->config.cayman.shader_engine_tile_size = 32;
704 rdev->config.cayman.num_gpus = 1;
705 rdev->config.cayman.multi_gpu_tile_size = 64;
706
707 //gb_addr_config = 0x02011003
708#if 0
709 gb_addr_config = RREG32(GB_ADDR_CONFIG);
710#else
711 gb_addr_config = 0;
712 switch (rdev->config.cayman.num_tile_pipes) {
713 case 1:
714 default:
715 gb_addr_config |= NUM_PIPES(0);
716 break;
717 case 2:
718 gb_addr_config |= NUM_PIPES(1);
719 break;
720 case 4:
721 gb_addr_config |= NUM_PIPES(2);
722 break;
723 case 8:
724 gb_addr_config |= NUM_PIPES(3);
725 break;
726 }
727
728 tmp = (rdev->config.cayman.mem_max_burst_length_bytes / 256) - 1;
729 gb_addr_config |= PIPE_INTERLEAVE_SIZE(tmp);
730 gb_addr_config |= NUM_SHADER_ENGINES(rdev->config.cayman.num_shader_engines - 1);
731 tmp = (rdev->config.cayman.shader_engine_tile_size / 16) - 1;
732 gb_addr_config |= SHADER_ENGINE_TILE_SIZE(tmp);
733 switch (rdev->config.cayman.num_gpus) {
734 case 1:
735 default:
736 gb_addr_config |= NUM_GPUS(0);
737 break;
738 case 2:
739 gb_addr_config |= NUM_GPUS(1);
740 break;
741 case 4:
742 gb_addr_config |= NUM_GPUS(2);
743 break;
744 }
745 switch (rdev->config.cayman.multi_gpu_tile_size) {
746 case 16:
747 gb_addr_config |= MULTI_GPU_TILE_SIZE(0);
748 break;
749 case 32:
750 default:
751 gb_addr_config |= MULTI_GPU_TILE_SIZE(1);
752 break;
753 case 64:
754 gb_addr_config |= MULTI_GPU_TILE_SIZE(2);
755 break;
756 case 128:
757 gb_addr_config |= MULTI_GPU_TILE_SIZE(3);
758 break;
759 }
760 switch (rdev->config.cayman.mem_row_size_in_kb) {
761 case 1:
762 default:
763 gb_addr_config |= ROW_SIZE(0);
764 break;
765 case 2:
766 gb_addr_config |= ROW_SIZE(1);
767 break;
768 case 4:
769 gb_addr_config |= ROW_SIZE(2);
770 break;
771 }
772#endif
773
774 tmp = (gb_addr_config & NUM_PIPES_MASK) >> NUM_PIPES_SHIFT;
775 rdev->config.cayman.num_tile_pipes = (1 << tmp);
776 tmp = (gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT;
777 rdev->config.cayman.mem_max_burst_length_bytes = (tmp + 1) * 256;
778 tmp = (gb_addr_config & NUM_SHADER_ENGINES_MASK) >> NUM_SHADER_ENGINES_SHIFT;
779 rdev->config.cayman.num_shader_engines = tmp + 1;
780 tmp = (gb_addr_config & NUM_GPUS_MASK) >> NUM_GPUS_SHIFT;
781 rdev->config.cayman.num_gpus = tmp + 1;
782 tmp = (gb_addr_config & MULTI_GPU_TILE_SIZE_MASK) >> MULTI_GPU_TILE_SIZE_SHIFT;
783 rdev->config.cayman.multi_gpu_tile_size = 1 << tmp;
784 tmp = (gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT;
785 rdev->config.cayman.mem_row_size_in_kb = 1 << tmp;
786
787 //gb_backend_map = 0x76541032;
788#if 0
789 gb_backend_map = RREG32(GB_BACKEND_MAP);
790#else
791 gb_backend_map =
792 cayman_get_tile_pipe_to_backend_map(rdev, rdev->config.cayman.num_tile_pipes,
793 rdev->config.cayman.num_backends_per_se *
794 rdev->config.cayman.num_shader_engines,
795 &rdev->config.cayman.backend_disable_mask_per_asic,
796 rdev->config.cayman.num_shader_engines);
797#endif
798 /* setup tiling info dword. gb_addr_config is not adequate since it does
799 * not have bank info, so create a custom tiling dword.
800 * bits 3:0 num_pipes
801 * bits 7:4 num_banks
802 * bits 11:8 group_size
803 * bits 15:12 row_size
804 */
805 rdev->config.cayman.tile_config = 0;
806 switch (rdev->config.cayman.num_tile_pipes) {
807 case 1:
808 default:
809 rdev->config.cayman.tile_config |= (0 << 0);
810 break;
811 case 2:
812 rdev->config.cayman.tile_config |= (1 << 0);
813 break;
814 case 4:
815 rdev->config.cayman.tile_config |= (2 << 0);
816 break;
817 case 8:
818 rdev->config.cayman.tile_config |= (3 << 0);
819 break;
820 }
821 rdev->config.cayman.tile_config |=
822 ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) << 4;
823 rdev->config.cayman.tile_config |=
824 (gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT;
825 rdev->config.cayman.tile_config |=
826 ((gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT) << 12;
827
828 WREG32(GB_BACKEND_MAP, gb_backend_map);
829 WREG32(GB_ADDR_CONFIG, gb_addr_config);
830 WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
831 WREG32(HDP_ADDR_CONFIG, gb_addr_config);
832
833 cayman_program_channel_remap(rdev);
834
835 /* primary versions */
836 WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
837 WREG32(CC_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable);
838 WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
839
840 WREG32(CGTS_TCC_DISABLE, cgts_tcc_disable);
841 WREG32(CGTS_SYS_TCC_DISABLE, cgts_tcc_disable);
842
843 /* user versions */
844 WREG32(GC_USER_RB_BACKEND_DISABLE, cc_rb_backend_disable);
845 WREG32(GC_USER_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable);
846 WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
847
848 WREG32(CGTS_USER_SYS_TCC_DISABLE, cgts_tcc_disable);
849 WREG32(CGTS_USER_TCC_DISABLE, cgts_tcc_disable);
850
851 /* reprogram the shader complex */
852 cgts_sm_ctrl_reg = RREG32(CGTS_SM_CTRL_REG);
853 for (i = 0; i < 16; i++)
854 WREG32(CGTS_SM_CTRL_REG, OVERRIDE);
855 WREG32(CGTS_SM_CTRL_REG, cgts_sm_ctrl_reg);
856
857 /* set HW defaults for 3D engine */
858 WREG32(CP_MEQ_THRESHOLDS, MEQ1_START(0x30) | MEQ2_START(0x60));
859
860 sx_debug_1 = RREG32(SX_DEBUG_1);
861 sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
862 WREG32(SX_DEBUG_1, sx_debug_1);
863
864 smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
865 smx_dc_ctl0 &= ~NUMBER_OF_SETS(0x1ff);
866 smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.evergreen.sx_num_of_sets);
867 WREG32(SMX_DC_CTL0, smx_dc_ctl0);
868
869 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4) | CRC_SIMD_ID_WADDR_DISABLE);
870
871 /* need to be explicitly zero-ed */
872 WREG32(VGT_OFFCHIP_LDS_BASE, 0);
873 WREG32(SQ_LSTMP_RING_BASE, 0);
874 WREG32(SQ_HSTMP_RING_BASE, 0);
875 WREG32(SQ_ESTMP_RING_BASE, 0);
876 WREG32(SQ_GSTMP_RING_BASE, 0);
877 WREG32(SQ_VSTMP_RING_BASE, 0);
878 WREG32(SQ_PSTMP_RING_BASE, 0);
879
880 WREG32(TA_CNTL_AUX, DISABLE_CUBE_ANISO);
881
882 WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_size / 4) - 1) |
883 POSITION_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_pos_size / 4) - 1) |
884 SMX_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_smx_size / 4) - 1)));
885
886 WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.evergreen.sc_prim_fifo_size) |
887 SC_HIZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_hiz_tile_fifo_size) |
888 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_earlyz_tile_fifo_size)));
889
890
891 WREG32(VGT_NUM_INSTANCES, 1);
892
893 WREG32(CP_PERFMON_CNTL, 0);
894
895 WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.evergreen.sq_num_cf_insts) |
896 FETCH_FIFO_HIWATER(0x4) |
897 DONE_FIFO_HIWATER(0xe0) |
898 ALU_UPDATE_FIFO_HIWATER(0x8)));
899
900 WREG32(SQ_GPR_RESOURCE_MGMT_1, NUM_CLAUSE_TEMP_GPRS(4));
901 WREG32(SQ_CONFIG, (VC_ENABLE |
902 EXPORT_SRC_C |
903 GFX_PRIO(0) |
904 CS1_PRIO(0) |
905 CS2_PRIO(1)));
906 WREG32(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, DYN_GPR_ENABLE);
907
908 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
909 FORCE_EOV_MAX_REZ_CNT(255)));
910
911 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC) |
912 AUTO_INVLD_EN(ES_AND_GS_AUTO));
913
914 WREG32(VGT_GS_VERTEX_REUSE, 16);
915 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
916
917 WREG32(CB_PERF_CTR0_SEL_0, 0);
918 WREG32(CB_PERF_CTR0_SEL_1, 0);
919 WREG32(CB_PERF_CTR1_SEL_0, 0);
920 WREG32(CB_PERF_CTR1_SEL_1, 0);
921 WREG32(CB_PERF_CTR2_SEL_0, 0);
922 WREG32(CB_PERF_CTR2_SEL_1, 0);
923 WREG32(CB_PERF_CTR3_SEL_0, 0);
924 WREG32(CB_PERF_CTR3_SEL_1, 0);
925
926 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
927 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
928
929 WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
930
931 udelay(50);
932}
933
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-11 10:15:13 -0500