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authorChristian König <deathsimple@vodafone.de>2012-08-09 10:21:08 -0400
committerAlex Deucher <alexander.deucher@amd.com>2012-09-20 13:10:39 -0400
commitee60e29f1dc650bf2239b757038973ef32f10878 (patch)
treef69c0ce143536212dd12690f4da87221af922e5b /drivers/gpu/drm/radeon/ni.c
parent9b40e5d8427f12567749978f66e86e5e8fced5ab (diff)
drm/radeon: rework VMID handling
Move binding onto the ring, simplifying handling a bit. Signed-off-by: Christian König <deathsimple@vodafone.de> Reviewed-by: Jerome Glisse <jglisse@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/ni.c')
-rw-r--r--drivers/gpu/drm/radeon/ni.c20
1 files changed, 11 insertions, 9 deletions
diff --git a/drivers/gpu/drm/radeon/ni.c b/drivers/gpu/drm/radeon/ni.c
index 8e3d70c7c9b7..de378d685803 100644
--- a/drivers/gpu/drm/radeon/ni.c
+++ b/drivers/gpu/drm/radeon/ni.c
@@ -1497,14 +1497,6 @@ void cayman_vm_fini(struct radeon_device *rdev)
1497{ 1497{
1498} 1498}
1499 1499
1500int cayman_vm_bind(struct radeon_device *rdev, struct radeon_vm *vm, int id)
1501{
1502 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR + (id << 2), 0);
1503 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR + (id << 2), vm->last_pfn);
1504 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (id << 2), vm->pt_gpu_addr >> 12);
1505 return 0;
1506}
1507
1508#define R600_PTE_VALID (1 << 0) 1500#define R600_PTE_VALID (1 << 0)
1509#define R600_PTE_SYSTEM (1 << 1) 1501#define R600_PTE_SYSTEM (1 << 1)
1510#define R600_PTE_SNOOPED (1 << 2) 1502#define R600_PTE_SNOOPED (1 << 2)
@@ -1540,10 +1532,20 @@ void cayman_vm_set_page(struct radeon_device *rdev, struct radeon_vm *vm,
1540void cayman_vm_flush(struct radeon_device *rdev, struct radeon_ib *ib) 1532void cayman_vm_flush(struct radeon_device *rdev, struct radeon_ib *ib)
1541{ 1533{
1542 struct radeon_ring *ring = &rdev->ring[ib->ring]; 1534 struct radeon_ring *ring = &rdev->ring[ib->ring];
1535 struct radeon_vm *vm = ib->vm;
1543 1536
1544 if (!ib->vm || ib->vm->id == -1) 1537 if (vm == NULL)
1545 return; 1538 return;
1546 1539
1540 radeon_ring_write(ring, PACKET0(VM_CONTEXT0_PAGE_TABLE_START_ADDR + (vm->id << 2), 0));
1541 radeon_ring_write(ring, 0);
1542
1543 radeon_ring_write(ring, PACKET0(VM_CONTEXT0_PAGE_TABLE_END_ADDR + (vm->id << 2), 0));
1544 radeon_ring_write(ring, vm->last_pfn);
1545
1546 radeon_ring_write(ring, PACKET0(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm->id << 2), 0));
1547 radeon_ring_write(ring, vm->pt_gpu_addr >> 12);
1548
1547 /* flush hdp cache */ 1549 /* flush hdp cache */
1548 radeon_ring_write(ring, PACKET0(HDP_MEM_COHERENCY_FLUSH_CNTL, 0)); 1550 radeon_ring_write(ring, PACKET0(HDP_MEM_COHERENCY_FLUSH_CNTL, 0));
1549 radeon_ring_write(ring, 0x1); 1551 radeon_ring_write(ring, 0x1);